{"id":"https://openalex.org/W3007522873","doi":"https://doi.org/10.1145/3373087.3375378","title":"MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows","display_name":"MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3007522873","doi":"https://doi.org/10.1145/3373087.3375378","mag":"3007522873"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375378","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375378","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047247727","display_name":"Pingakshya Goswami","orcid":"https://orcid.org/0000-0003-0614-6599"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pingakshya Goswami","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048938287","display_name":"Masoud Shahshahani","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Masoud Shahshahani","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069692759","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0002-5019-7417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Bhatia","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5047247727"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.4621,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.55821719,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"312","last_page":"312"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7846789360046387},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5695117712020874},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5406396389007568},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5174891948699951},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.46263402700424194},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.45482969284057617},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45242205262184143},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.411824494600296},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4024856984615326}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7846789360046387},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5695117712020874},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5406396389007568},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5174891948699951},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.46263402700424194},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.45482969284057617},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45242205262184143},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.411824494600296},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4024856984615326},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375378","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375378","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W2091330445","https://openalex.org/W3011978806","https://openalex.org/W3204573923","https://openalex.org/W2160632767","https://openalex.org/W3207169898","https://openalex.org/W2743305891","https://openalex.org/W2019954703","https://openalex.org/W4385309418","https://openalex.org/W3198354237"],"abstract_inverted_index":{"With":[0],"the":[1,12,19,31,34,38,48,73,77,92,110,115,161,164,173,202],"advent":[2],"of":[3,16,33,53,69,72,94,99,114,127],"Machine":[4],"Learning":[5],"(ML),":[6],"predictive":[7,116],"EDA":[8,20,35],"tools":[9,28,60],"are":[10,24,103,176,188],"becoming":[11],"next":[13],"hot":[14],"topic":[15],"research":[17],"in":[18,61,82,91,133,163],"community,":[21],"and":[22,63,112,135,159,171],"researchers":[23],"working":[25],"on":[26],"ML-based":[27],"to":[29,46,108,141,182,191],"predict":[30],"performance":[32,97,111],"tool.":[36],"As":[37],"designs":[39,131,143,158,175],"become":[40],"complex,":[41],"there":[42,102],"is":[43,167],"a":[44,125,139,148,153,192],"need":[45],"start":[47],"design":[49,65,75,84,203],"using":[50,208],"higher":[51],"levels":[52],"abstraction,":[54],"such":[55],"as":[56],"High-Level":[57],"Synthesis":[58],"(HLS)":[59],"FPGA":[62],"SoC":[64],"flows.":[66],"Quick":[67],"prediction":[68,98],"performance-related":[70],"parameters":[71],"final":[74],"after":[76],"C-synthesis":[78],"stage,":[79],"can":[80],"help":[81],"rapid":[83],"closure.":[85],"Even":[86],"though":[87],"multiple":[88],"papers":[89],"exist":[90],"domain":[93],"post":[95],"routing":[96],"HLS":[100,210],"tools,":[101],"no":[104],"standard":[105],"benchmarks":[106],"available":[107],"compare":[109],"accuracy":[113],"models.":[117],"In":[118],"this":[119],"paper,":[120],"we":[121],"have":[122],"presented":[123],"MLSBench,":[124],"collection":[126],"around":[128],"5000":[129],"synthesizable":[130],"written":[132],"C":[134],"C++.":[136],"We":[137,195],"provide":[138],"methodology":[140],"generate":[142],"with":[144],"various":[145],"variations":[146],"from":[147],"single":[149],"design,":[150],"which":[151],"creates":[152],"potential":[154],"for":[155,200,211],"creating":[156],"newer":[157],"enlarging":[160],"database":[162],"future.":[165],"This":[166,179],"followed":[168],"by":[169,205],"analysis,":[170],"validating":[172],"generated":[174],"indeed":[177],"different.":[178],"allows":[180],"designers":[181],"create":[183],"generalized":[184],"machine-learning-based":[185],"models":[186],"that":[187],"not":[189],"overfitted":[190],"small":[193],"dataset.":[194],"also":[196],"perform":[197],"statistical":[198],"analysis":[199],"measuring":[201],"diversity":[204],"synthesizing":[206],"them":[207],"Xilinx-Vivado":[209],"Zynq":[212],"7000":[213],"device":[214],"series.":[215]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}