{"id":"https://openalex.org/W3007295933","doi":"https://doi.org/10.1145/3373087.3375372","title":"INTB: A New FPGA Interconnect Model for Architecture Exploration","display_name":"INTB: A New FPGA Interconnect Model for Architecture Exploration","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3007295933","doi":"https://doi.org/10.1145/3373087.3375372","mag":"3007295933"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375372","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014548453","display_name":"Chengyu Hu","orcid":"https://orcid.org/0000-0001-8226-5747"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chengyu Hu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000918972","display_name":"Qinghua Duan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qinghua Duan","raw_affiliation_strings":["Chengdu Sino Microelectronic Technology Co., Ltd, Chengdu, China"],"affiliations":[{"raw_affiliation_string":"Chengdu Sino Microelectronic Technology Co., Ltd, Chengdu, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025981776","display_name":"Peng Lu","orcid":"https://orcid.org/0000-0003-0743-1068"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Lu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100431706","display_name":"Wei Liu","orcid":"https://orcid.org/0000-0001-9439-5100"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Liu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5014548453"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01243303,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"325","last_page":"325"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7751919031143188},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.757577657699585},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7020797729492188},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6391476392745972},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.6283257007598877},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5449451804161072},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48823311924934387},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48509156703948975},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4443952441215515},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42252397537231445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36419349908828735},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14739328622817993},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14105328917503357},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.1354784071445465},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07987087965011597}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7751919031143188},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.757577657699585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7020797729492188},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6391476392745972},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.6283257007598877},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5449451804161072},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48823311924934387},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48509156703948975},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4443952441215515},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42252397537231445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36419349908828735},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14739328622817993},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14105328917503357},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.1354784071445465},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07987087965011597},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375372","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2037960874","https://openalex.org/W2091330445","https://openalex.org/W4313341326","https://openalex.org/W1973069902","https://openalex.org/W2269990635","https://openalex.org/W1968547622","https://openalex.org/W4234221021","https://openalex.org/W1567432572","https://openalex.org/W2119904701","https://openalex.org/W2159184138"],"abstract_inverted_index":{"CAD":[0,29,115,167,195],"exploration":[1],"is":[2,56,118,128,137,183,207,215],"important":[3],"for":[4,148],"designing":[5],"FPGA":[6,101,223],"interconnect":[7,35,44,82],"topologies.":[8],"It":[9],"includes":[10],"two":[11,110,178,205],"steps:":[12],"first,":[13],"design":[14],"a":[15,42,51],"model":[16,78,165,182,214],"with":[17,73,221],"some":[18,234],"parameters":[19,66],"that":[20],"can":[21,79,99],"express":[22],"as":[23,88],"much":[24],"architecture":[25,219],"space.":[26],"Second,":[27,212],"use":[28],"flow":[30],"to":[31,58,69,130,185,189,217],"analyze":[32],"the":[33,105],"described":[34],"architecture.":[36],"In":[37],"this":[38],"paper,":[39],"we":[40],"present":[41],"new":[43],"model,":[45,76,109],"named":[46],"INTB":[47,55,77,108,164,181,213],"(Interconnect":[48],"Block).":[49],"At":[50],"logical":[52],"position,":[53],"one":[54,117],"adopted":[57,184],"represent":[59],"all":[60],"related":[61],"routing":[62,102,121,141,200],"resources":[63],"and":[64,94,153,166,202,210],"hierarchical":[65],"are":[67,112,145,169],"designed":[68],"simplify":[70],"description.":[71],"Compared":[72],"existing":[74],"CB-SB":[75,162,187],"support":[80],"more":[81],"features":[83,98],"of":[84,91,107,120,151,177,199],"modern":[85,222],"FPGA,":[86],"such":[87],"various":[89],"types":[90],"wire":[92,155],"segment":[93],"complex":[95],"connections.":[96],"These":[97],"improve":[100],"ability.":[103],"For":[104],"application":[106],"modifications":[111],"made":[113],"in":[114,161,171,233],"flow:":[116],"generation":[119],"resource":[122],"graph":[123],"(RRG).":[124],"A":[125],"tile-based":[126],"method":[127],"proposed":[129],"generate":[131],"RRG":[132],"from":[133],"parameters.":[134],"The":[135,174],"other":[136],"cost":[138,149],"computing":[139],"during":[140],"process.":[142],"Two":[143],"strategies":[144],"applied":[146],"respectively":[147],"estimation":[150],"short":[152],"curve":[154],"segment,":[156],"which":[157],"do":[158],"not":[159],"exist":[160],"model.":[163],"improvement":[168],"implemented":[170],"VTR":[172],"8.0.":[173],"experiments":[175],"consist":[176],"parts.":[179],"First,":[180],"re-describe":[186],"architectures":[188],"verify":[190],"its":[191],"description":[192],"capacity.":[193],"After":[194],"flow,":[196],"average":[197],"difference":[198],"area":[201],"timing":[203],"between":[204],"models":[206],"about":[208],"4%":[209],"5%.":[211],"used":[216],"explore":[218],"space":[220],"features.":[224],"Experimental":[225],"results":[226],"show":[227],"obvious":[228],"performance":[229],"enhancement,":[230],"over":[231],"10%":[232],"benchmarks.":[235]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
