{"id":"https://openalex.org/W3007162293","doi":"https://doi.org/10.1145/3373087.3375367","title":"R2CNN: Recurrent Residual Convolutional Neural Network on FPGA","display_name":"R2CNN: Recurrent Residual Convolutional Neural Network on FPGA","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3007162293","doi":"https://doi.org/10.1145/3373087.3375367","mag":"3007162293"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375367","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375367","pdf_url":null,"source":{"id":"https://openalex.org/S7407087960","display_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070734898","display_name":"Hiroki Nakahara","orcid":"https://orcid.org/0000-0002-5701-7466","observed_orcids":["https://orcid.org/0000-0002-5701-7466"]},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698","https://openalex.org/I4400009020"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroki Nakahara","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Que Zhiqiang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Que Zhiqiang","raw_affiliation_strings":["Imperial College Longon, Longon, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College Longon, Longon, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016922897","display_name":"Akira Jinguji","orcid":"https://orcid.org/0000-0001-5691-3472","observed_orcids":["https://orcid.org/0000-0001-5691-3472"]},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698","https://openalex.org/I4400009020"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Jinguji","raw_affiliation_strings":["Tokyo Institute of Technology, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne W. Luk","orcid":"https://orcid.org/0000-0002-6750-927X","observed_orcids":["https://orcid.org/0000-0002-6750-927X"]},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"319","last_page":"319"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9398999810218811,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9398999810218811,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.05380000174045563,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.003100000089034438,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.6520000100135803},{"id":"https://openalex.org/keywords/convolutional-neural-network-accelerator","display_name":"convolutional neural network accelerator","score":0.6399999856948853},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.6639999747276306},{"id":"https://openalex.org/keywords/imagenet-classification","display_name":"ImageNet classification","score":0.7300000190734863},{"id":"https://openalex.org/keywords/ventral-stream","display_name":"ventral stream","score":0.8069999814033508}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.779279351234436},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7548757791519165},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.7467980980873108},{"id":"https://openalex.org/C155512373","wikidata":"https://www.wikidata.org/wiki/Q287450","display_name":"Residual","level":2,"score":0.7166998386383057},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.5225414633750916},{"id":"https://openalex.org/C2776214188","wikidata":"https://www.wikidata.org/wiki/Q408386","display_name":"Inference","level":2,"score":0.5143407583236694},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5007209777832031},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.49878430366516113},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.4637983441352844},{"id":"https://openalex.org/C147168706","wikidata":"https://www.wikidata.org/wiki/Q1457734","display_name":"Recurrent neural network","level":3,"score":0.4536159038543701},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39559993147850037},{"id":"https://openalex.org/C153180895","wikidata":"https://www.wikidata.org/wiki/Q7148389","display_name":"Pattern recognition (psychology)","level":2,"score":0.3510051369667053},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.31461188197135925},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24166199564933777},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1963425576686859},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375367","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375367","pdf_url":null,"source":{"id":"https://openalex.org/S7407087960","display_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[],"study_designs":[],"awards":[{"id":"https://openalex.org/G4587427570","display_name":null,"funder_award_id":"EP/S030069/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7493804148","display_name":null,"funder_award_id":"EP/N031768/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4298287631","https://openalex.org/W2953061907","https://openalex.org/W2790400419","https://openalex.org/W3034421924","https://openalex.org/W2982536526","https://openalex.org/W4386858688","https://openalex.org/W4380302312","https://openalex.org/W3008689640","https://openalex.org/W4385338604","https://openalex.org/W3081626085"],"abstract_inverted_index":{"Over":[0],"the":[1,41,46,53,78,139],"past":[2],"years,":[3],"feed-forward":[4,14],"convolutional":[5,111],"neural":[6,35,112],"networks":[7],"(CNNs)":[8],"have":[9],"evolved":[10],"from":[11,40],"a":[12,132,143],"simple":[13],"architecture":[15,107],"to":[16,65],"deep":[17,50],"and":[18,28,36,52,93],"residual":[19,110,134],"(skip-connection)":[20],"architectures,":[21],"demonstrating":[22],"increasingly":[23,29],"higher":[24,100,165],"object":[25],"categorization":[26],"accuracy":[27,101,156,166],"better":[30],"explanatory":[31],"power":[32],"of":[33,44,157],"both":[34],"behavioral":[37],"responses.":[38],"However,":[39],"neuroscientist":[42],"point":[43],"view,":[45],"relationship":[47],"between":[48],"such":[49],"architectures":[51,92],"ventral":[54],"visual":[55],"pathway":[56],"is":[57],"incomplete.":[58],"For":[59],"example,":[60],"current":[61],"state-of-the-art":[62],"CNNs":[63,88],"appear":[64],"be":[66],"too":[67],"complex":[68],"(e.g.,":[69],"now":[70],"over":[71],"100":[72],"layers":[73],"for":[74,102,108,131],"ResNet)":[75],"compared":[76],"with":[77,89,148],"relatively":[79],"shallow":[80,90],"cortical":[81],"hierarchy":[82],"(4-8":[83],"layers).":[84],"We":[85,123,137],"introduce":[86],"new":[87],"recurrent":[91,109,133],"skip":[94],"connections":[95],"requiring":[96],"fewer":[97],"parameters.":[98],"With":[99],"classification,":[103],"we":[104],"propose":[105,124],"an":[106,125],"network":[113],"(R2CNN)":[114],"on":[115,142,159],"FPGA,":[116],"which":[117,163],"efficiently":[118],"utilizes":[119],"on-chip":[120],"memory":[121],"bandwidth.":[122],"Output-Kernel-":[126],"Input-Parallel":[127],"(OKIP)":[128],"convolution":[129,135],"circuit":[130],"stage.":[136],"implement":[138],"inference":[140],"hardware":[141],"Xilinx":[144],"ZCU104":[145],"evaluation":[146],"board":[147],"high-level":[149],"synthesis.":[150],"Our":[151],"R2CNN":[152],"accelerator":[153],"achieves":[154],"top-5":[155],"90.08%":[158],"ImageNet":[160],"bench-":[161],"mark,":[162],"has":[164],"than":[167],"conventional":[168],"FPGA":[169],"implementations.":[170]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-10-05T09:50:58.205359","created_date":"2025-10-10T00:00:00"}