{"id":"https://openalex.org/W3008956087","doi":"https://doi.org/10.1145/3373087.3375362","title":"Performance Portable FPGA Design","display_name":"Performance Portable FPGA Design","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3008956087","doi":"https://doi.org/10.1145/3373087.3375362","mag":"3008956087"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375362","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072095076","display_name":"Nils Voss","orcid":"https://orcid.org/0000-0001-7466-4545"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Nils Voss","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086939715","display_name":"Tobias Becker","orcid":"https://orcid.org/0000-0001-5939-6757"},"institutions":[{"id":"https://openalex.org/I4210143063","display_name":"Maxeler Technologies (United Kingdom)","ror":"https://ror.org/05bm26z17","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210143063"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Tobias Becker","raw_affiliation_strings":["Maxeler Technologies, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Maxeler Technologies, London, United Kingdom","institution_ids":["https://openalex.org/I4210143063"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057057077","display_name":"Simon Tilbury","orcid":null},"institutions":[{"id":"https://openalex.org/I4210143063","display_name":"Maxeler Technologies (United Kingdom)","ror":"https://ror.org/05bm26z17","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210143063"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon Tilbury","raw_affiliation_strings":["Maxeler Technologies, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Maxeler Technologies, London, United Kingdom","institution_ids":["https://openalex.org/I4210143063"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075050234","display_name":"Georgi Gaydadjiev","orcid":"https://orcid.org/0000-0002-3678-7007"},"institutions":[{"id":"https://openalex.org/I4210143063","display_name":"Maxeler Technologies (United Kingdom)","ror":"https://ror.org/05bm26z17","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210143063"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Georgi Gaydadjiev","raw_affiliation_strings":["Maxeler Technologies, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Maxeler Technologies, London, United Kingdom","institution_ids":["https://openalex.org/I4210143063"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083608463","display_name":"Oskar Mencer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210143063","display_name":"Maxeler Technologies (United Kingdom)","ror":"https://ror.org/05bm26z17","country_code":"GB","type":"company","lineage":["https://openalex.org/I4210143063"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Oskar Mencer","raw_affiliation_strings":["Maxeler Technologies, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Maxeler Technologies, London, United Kingdom","institution_ids":["https://openalex.org/I4210143063"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110815532","display_name":"Anna Maria Nestorov","orcid":"https://orcid.org/0000-0003-3233-0322"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Anna Maria Nestorov","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064165125","display_name":"Enrico Reggiani","orcid":"https://orcid.org/0000-0003-1385-7962"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Enrico Reggiani","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5072095076"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":0.9241,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.70484901,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"324","last_page":"324"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.8938155174255371},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.843217134475708},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.84033203125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8042211532592773},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7457820773124695},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6533360481262207},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.4843672215938568},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4695252478122711},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40080296993255615},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.35076749324798584},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3506406843662262}],"concepts":[{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.8938155174255371},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.843217134475708},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.84033203125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8042211532592773},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7457820773124695},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6533360481262207},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.4843672215938568},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4695252478122711},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40080296993255615},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.35076749324798584},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3506406843662262},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375362","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375362","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1820309981","https://openalex.org/W3124707092","https://openalex.org/W2375332572","https://openalex.org/W28826848","https://openalex.org/W3123383020","https://openalex.org/W4312942606","https://openalex.org/W2166776054","https://openalex.org/W2912579397","https://openalex.org/W2152694830","https://openalex.org/W1662038552"],"abstract_inverted_index":{"FPGA":[0,71,176],"platforms":[1,22,95,171],"are":[2],"widely":[3],"used":[4],"for":[5,35,67,225],"application":[6,16,46,119,165,194],"acceleration.":[7],"Although":[8],"a":[9,62,86,105,138,167,190],"number":[10,168],"of":[11,126,150,162,169,227],"high-level":[12,36,87],"design":[13,34,51],"frameworks":[14],"exist,":[15],"and":[17,185,210],"performance":[18,56,141,148,218],"portability":[19],"across":[20,166],"different":[21,170,198],"remain":[23],"challenging.":[24],"To":[25,58],"address":[26],"the":[27,44,93,114,118,127,132,155,163,174,186,192,211],"above":[28],"problem,":[29],"we":[30,49,158],"propose":[31,50],"an":[32,68,146],"API":[33],"development":[37],"tools":[38],"to":[39,53,74,109,123,152,220],"separate":[40],"platform-dependent":[41],"code":[42,103,195],"from":[43],"remaining":[45],"design.":[47],"Additionally,":[48],"guidelines":[52],"assist":[54],"with":[55,96,217],"portability.":[57],"demonstrate":[59,159],"our":[60],"techniques,":[61],"large-scale":[63],"application,":[64,83],"originally":[65],"developed":[66,84],"Intel":[69,213],"Stratix-V":[70,214],"is":[72,89,120,222],"ported":[73],"several":[75],"new":[76,94,115],"Xilinx":[77,206],"Virtex":[78],"UltraScale+":[79],"systems.":[80],"The":[81,99],"accelerated":[82],"in":[85,145,180],"framework,":[88,157],"rapidly":[90],"moved":[91],"onto":[92],"minimal":[97],"changes.":[98],"original,":[100],"unmodified":[101],"kernel":[102],"delivers":[104],"1.74x":[106],"speedup":[107],"due":[108],"increased":[110],"clock":[111],"frequency":[112],"on":[113,131],"platform.":[116],"Subsequently,":[117],"further":[121],"optimised":[122],"make":[124],"use":[125],"additional":[128,147],"resources":[129],"available":[130,187],"larger":[133],"Ultrascale+":[134],"FPGAs,":[135],"guided":[136],"by":[137],"simple":[139],"analytical":[140],"model.":[142],"This":[143],"results":[144],"increase":[149],"up":[151],"7.4x.":[153],"Using":[154],"presented":[156],"rapid":[160],"deployment":[161],"same":[164,175,193],"that":[172],"leverage":[173],"family":[177],"but":[178],"differ":[179],"their":[181],"low-level":[182],"implementation":[183],"details":[184],"peripherals.":[188],"As":[189],"result,":[191],"supports":[196],"five":[197],"platforms:":[199],"Maxeler":[200],"MAX5C":[201],"DFE,":[202],"Amazon":[203],"EC2":[204],"F1,":[205],"Alveo":[207],"U200,":[208],"U250":[209],"original":[212],"accelerator":[215],"card,":[216],"close":[219],"what":[221],"theoretically":[223],"achievable":[224],"each":[226],"these":[228],"platforms.":[229]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}