{"id":"https://openalex.org/W3008197904","doi":"https://doi.org/10.1145/3373087.3375338","title":"Productive Hardware Designs using Hybrid HLS-RTL Development","display_name":"Productive Hardware Designs using Hybrid HLS-RTL Development","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3008197904","doi":"https://doi.org/10.1145/3373087.3375338","mag":"3008197904"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375338","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032876321","display_name":"Blaise Tine","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Blaise Tine","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090962911","display_name":"Seyong Lee","orcid":"https://orcid.org/0000-0001-8872-4932"},"institutions":[{"id":"https://openalex.org/I1289243028","display_name":"Oak Ridge National Laboratory","ror":"https://ror.org/01qz5mb56","country_code":"US","type":"facility","lineage":["https://openalex.org/I1289243028","https://openalex.org/I1330989302","https://openalex.org/I39565521","https://openalex.org/I4210159294"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Seyong Lee","raw_affiliation_strings":["Oak Ridge National Laboratory, Oak Ridge, TN, USA"],"affiliations":[{"raw_affiliation_string":"Oak Ridge National Laboratory, Oak Ridge, TN, USA","institution_ids":["https://openalex.org/I1289243028"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111669766","display_name":"Jeff Vetter","orcid":null},"institutions":[{"id":"https://openalex.org/I1289243028","display_name":"Oak Ridge National Laboratory","ror":"https://ror.org/01qz5mb56","country_code":"US","type":"facility","lineage":["https://openalex.org/I1289243028","https://openalex.org/I1330989302","https://openalex.org/I39565521","https://openalex.org/I4210159294"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeff Vetter","raw_affiliation_strings":["Oak Ridge National Laboratory, Oak Ridge, TN, USA"],"affiliations":[{"raw_affiliation_string":"Oak Ridge National Laboratory, Oak Ridge, TN, USA","institution_ids":["https://openalex.org/I1289243028"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000822269","display_name":"Hyesoon Kim","orcid":"https://orcid.org/0000-0002-6061-7825"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyesoon Kim","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5032876321"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02787456,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"311","last_page":"311"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7813109159469604},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6757761240005493},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.6102735996246338},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.5890913605690002},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5837021470069885},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5815080404281616},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5547173619270325},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5280673503875732},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36602523922920227},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2927094101905823}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7813109159469604},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6757761240005493},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.6102735996246338},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.5890913605690002},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5837021470069885},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5815080404281616},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5547173619270325},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5280673503875732},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36602523922920227},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2927094101905823},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375338","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2612099726","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160632767","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W2000188956","https://openalex.org/W1973862904","https://openalex.org/W181593118"],"abstract_inverted_index":{"Current":[0],"High-Level":[1],"Synthesis":[2],"frameworks":[3,37],"provide":[4],"a":[5,77,99],"productive":[6,53],"hardware":[7,11,33,57],"development":[8,48,105],"methodology":[9],"where":[10],"accelerators":[12],"are":[13],"generated":[14,34],"directly":[15],"from":[16],"high-level":[17],"languages":[18],"like":[19],"C/C++":[20],"or":[21],"OpenCL,":[22],"allowing":[23],"software":[24,54],"developers":[25],"to":[26,41,102],"quickly":[27],"accelerate":[28],"their":[29],"applications.":[30],"However,":[31],"the":[32,52,104],"by":[35],"these":[36],"is":[38],"sub-optimal":[39],"compared":[40],"often":[42],"hand-optimized":[43],"RTL":[44,70,86],"modules.":[45],"A":[46],"hybrid":[47],"approach":[49],"would":[50],"leverage":[51],"stack":[55],"and":[56],"board":[58],"support":[59],"package":[60],"that":[61,82],"HLS":[62],"provides":[63],"but":[64],"allow":[65],"for":[66],"fine-grained":[67],"optimization":[68],"using":[69],"components.":[71],"In":[72],"this":[73],"work,":[74],"we":[75],"introduce":[76],"new":[78],"software-hardware":[79],"co-design":[80],"framework":[81],"integrates":[83],"OpenCL/OpenACC":[84],"with":[85,98],"code":[87],"enabling":[88],"direct":[89],"execution":[90],"on":[91],"FPGAs":[92],"as":[93,95],"well":[94],"full":[96],"emulation":[97],"high-speed":[100],"simulator":[101],"reduce":[103],"time.":[106]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
