{"id":"https://openalex.org/W3008410827","doi":"https://doi.org/10.1145/3373087.3375310","title":"Finding and Understanding Bugs in FPGA Synthesis Tools","display_name":"Finding and Understanding Bugs in FPGA Synthesis Tools","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3008410827","doi":"https://doi.org/10.1145/3373087.3375310","mag":"3008410827"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375310","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085695502","display_name":"Yann Herklotz","orcid":"https://orcid.org/0000-0002-2329-1029"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Yann Herklotz","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002846450","display_name":"John Wickerson","orcid":"https://orcid.org/0000-0001-6735-5533"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John Wickerson","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5085695502"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":4.1621,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.9385083,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"277","last_page":"287"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12423","display_name":"Software Reliability and Analysis Research","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7929752469062805},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.792499840259552},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7308413982391357},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.694359540939331},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6080461740493774},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.5997820496559143},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5257611870765686},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4850463271141052},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4718477725982666},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.44655129313468933},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.41030627489089966},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.39618155360221863},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.34976956248283386},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.34947115182876587}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7929752469062805},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.792499840259552},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7308413982391357},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.694359540939331},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6080461740493774},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.5997820496559143},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5257611870765686},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4850463271141052},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4718477725982666},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.44655129313468933},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.41030627489089966},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.39618155360221863},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.34976956248283386},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.34947115182876587},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3373087.3375310","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/75755","is_oa":false,"landing_page_url":"http://hdl.handle.net/10044/1/75755","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.550000011920929,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G1641431731","display_name":null,"funder_award_id":"EP/R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5938769023","display_name":null,"funder_award_id":"VeTSS","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6480646621","display_name":"Interface reasoning for interacting systems (IRIS).","funder_award_id":"EP/R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8840470266","display_name":null,"funder_award_id":"R006865/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W109452506","https://openalex.org/W1966021031","https://openalex.org/W2098456636","https://openalex.org/W2121217767","https://openalex.org/W2128057448","https://openalex.org/W2128600579","https://openalex.org/W2129695855","https://openalex.org/W2155877593","https://openalex.org/W2159595840","https://openalex.org/W2165436148","https://openalex.org/W2170224888","https://openalex.org/W2188922879","https://openalex.org/W2492810892","https://openalex.org/W2753285289","https://openalex.org/W2795150074","https://openalex.org/W2953840721","https://openalex.org/W3208377248","https://openalex.org/W4238083723"],"related_works":["https://openalex.org/W21388859","https://openalex.org/W3046927439","https://openalex.org/W2360029815","https://openalex.org/W2543290882","https://openalex.org/W4235515009","https://openalex.org/W2171413119","https://openalex.org/W2788911029","https://openalex.org/W2125763413","https://openalex.org/W4234123702","https://openalex.org/W2895905110"],"abstract_inverted_index":{"All":[0],"software":[1],"ultimately":[2],"relies":[3],"on":[4,28,42],"hardware":[5,35],"functioning":[6],"correctly.":[7],"Hardware":[8],"correctness":[9,47],"is":[10,51,89],"becoming":[11],"increasingly":[12],"important":[13],"due":[14],"to":[15,24,38,62,74,92,124,170,181,192,204],"the":[16,31,46,54,57,64,86,93,126,129,152,174,177],"growing":[17],"use":[18],"of":[19,34,48,56,66,99,113,128,151,188,207],"custom":[20],"accelerators":[21],"using":[22,78],"FPGAs":[23],"speed":[25],"up":[26],"applications":[27],"servers.":[29],"Furthermore,":[30],"increasing":[32],"complexity":[33],"also":[36,144],"leads":[37],"ever":[39],"more":[40],"reliance":[41],"automation,":[43],"meaning":[44],"that":[45,85,131],"synthesis":[49,68,163],"tools":[50,69],"vital":[52],"for":[53,107],"reliability":[55],"hardware.":[58],"This":[59,142],"paper":[60,143],"aims":[61],"improve":[63],"quality":[65],"FPGA":[67],"by":[70],"introducing":[71],"a":[72,105,118,138,146,185],"method":[73,106],"test":[75,120],"them":[76],"automatically":[77],"randomly":[79],"generated,":[80],"correct":[81],"Verilog,":[82],"and":[83,116,148,159,176,184],"checking":[84],"synthesised":[87],"netlist":[88,175],"always":[90],"equivalent":[91],"original":[94],"design.":[95,178],"The":[96],"main":[97],"contributions":[98],"this":[100],"work":[101],"are":[102,135],"twofold:":[103],"firstly":[104],"generating":[108],"random":[109],"behavioural":[110],"Verilog":[111,119],"free":[112],"undefined":[114],"values,":[115],"secondly":[117],"case":[121],"reducer":[122],"used":[123],"locate":[125],"cause":[127],"bug":[130],"was":[132,168],"found.":[133],"These":[134],"implemented":[136],"in":[137,155],"tool":[139,164,205],"called":[140],"Verismith.":[141],"provides":[145],"qualitative":[147],"quantitative":[149],"analysis":[150],"bugs":[153,201],"found":[154,169,191],"Yosys,":[156],"Vivado,":[157],"XST":[158],"Quartus":[160,166],"Prime.":[161],"Every":[162],"except":[165],"Prime":[167],"introduce":[171],"discrepancies":[172],"between":[173],"In":[179],"addition":[180],"that,":[182],"Vivado":[183],"development":[186],"version":[187],"Yosys":[189],"were":[190,202],"crash":[193],"when":[194],"given":[195],"valid":[196],"input.":[197],"Using":[198],"Verismith,":[199],"eleven":[200],"reported":[203],"vendors,":[206],"which":[208],"six":[209],"have":[210],"already":[211],"been":[212],"fixed.":[213]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":14},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2020-03-06T00:00:00"}