{"id":"https://openalex.org/W3008619650","doi":"https://doi.org/10.1145/3373087.3375308","title":"Architectural Enhancements in Intel\u00ae Agilex\u2122 FPGAs","display_name":"Architectural Enhancements in Intel\u00ae Agilex\u2122 FPGAs","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3008619650","doi":"https://doi.org/10.1145/3373087.3375308","mag":"3008619650"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375308","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041764533","display_name":"Jeffrey Chromczak","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jeffrey Chromczak","raw_affiliation_strings":["Intel Corporation, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080078149","display_name":"Mark Wheeler","orcid":"https://orcid.org/0000-0003-0562-7032"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mark Wheeler","raw_affiliation_strings":["Intel Corporation, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074708905","display_name":"Charles Chiasson","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Charles Chiasson","raw_affiliation_strings":["Intel Corporation, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Toronto, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031787837","display_name":"Dana How","orcid":"https://orcid.org/0000-0003-2843-1972"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dana How","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082265695","display_name":"Martin Langhammer","orcid":"https://orcid.org/0000-0001-8206-2077"},"institutions":[{"id":"https://openalex.org/I2801054121","display_name":"Coeliac UK","ror":"https://ror.org/042404z19","country_code":"GB","type":"nonprofit","lineage":["https://openalex.org/I2801054121"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Martin Langhammer","raw_affiliation_strings":["Intel Corporation, High Wycombe, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, High Wycombe, United Kingdom","institution_ids":["https://openalex.org/I2801054121","https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035149504","display_name":"Tim Vanderhoek","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tim Vanderhoek","raw_affiliation_strings":["Intel Corporation, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Toronto, ON, Canada","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028606671","display_name":"Grace Zgheib","orcid":"https://orcid.org/0000-0002-1476-2984"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Grace Zgheib","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091859340","display_name":"Ilya Ganusov","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ilya Ganusov","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5041764533"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.3723,"has_fulltext":false,"cited_by_count":61,"citation_normalized_percentile":{"value":0.94562006,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"140","last_page":"149"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7139012813568115},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6991362571716309},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6422433853149414},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.5892339944839478},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5756623148918152},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.528694748878479},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.46241116523742676},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4376608431339264},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42544299364089966},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40157321095466614},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20583102107048035}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7139012813568115},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6991362571716309},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6422433853149414},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.5892339944839478},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5756623148918152},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.528694748878479},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.46241116523742676},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4376608431339264},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42544299364089966},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40157321095466614},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20583102107048035},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3373087.3375308","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375308","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5400000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W12081373","https://openalex.org/W1491307824","https://openalex.org/W2007049691","https://openalex.org/W2011778848","https://openalex.org/W2023146792","https://openalex.org/W2038318386","https://openalex.org/W2061488635","https://openalex.org/W2116094656","https://openalex.org/W2161125053","https://openalex.org/W2207050309","https://openalex.org/W2264331490","https://openalex.org/W2277819611","https://openalex.org/W2464089552","https://openalex.org/W2787310733","https://openalex.org/W2951989312"],"related_works":["https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W3208151864","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W1564576805","https://openalex.org/W2014521732","https://openalex.org/W3012528295","https://openalex.org/W2024574431","https://openalex.org/W4254372399"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"architectural":[3],"enhancements":[4,53],"in":[5,81],"Intel\u00ae":[6],"Agilex\u2122":[7],"FPGAs":[8],"and":[9,19,37,40,59,85,100,130],"SoCs.":[10],"Agilex":[11,47],"devices":[12],"are":[13,72,117],"built":[14],"on":[15],"Intel's":[16],"10nm":[17],"process":[18,129],"feature":[20],"next-generation":[21],"programmable":[22,97],"fabric,":[23],"tightly":[24],"coupled":[25],"with":[26,63,88,128],"a":[27,32,89],"quad-core":[28],"ARM":[29],"processor":[30],"subsystem,":[31],"secure":[33],"device":[34],"manager,":[35],"IO":[36],"memory":[38],"interfaces,":[39],"multiple":[41,50],"companion":[42],"transceiver":[43],"tile":[44],"choices.":[45],"The":[46],"fabric":[48,106],"features":[49],"logic":[51],"block":[52],"that":[54],"significantly":[55],"improve":[56],"propagation":[57],"delays":[58],"integrate":[60],"more":[61,136],"effectively":[62],"the":[64,105,109,142],"second-generation":[65],"HyperFlexAgilex\u2122":[66],"pipelined":[67],"routing":[68],"architecture.":[69],"Routing":[70],"connections":[71,79],"re-designed":[73],"to":[74,107,120],"be":[75],"point-to-point,":[76],"dropping":[77],"intermediate":[78],"featured":[80],"prior":[82],"FPGA":[83],"generations":[84],"replacing":[86],"them":[87],"wider":[90],"variety":[91],"of":[92,112,146],"shorter":[93],"wire":[94],"types.":[95],"Fine-grain":[96],"clock":[98],"skew":[99],"time-borrowing":[101],"were":[102],"introduced":[103],"throughout":[104],"augment":[108],"slack-balancing":[110],"capabilities":[111,116],"HyperFlex":[113],"registers.":[114],"DSP":[115],"also":[118],"extended":[119],"natively":[121],"support":[122,135],"new":[123],"INT9/BFLOAT16/FP16":[124],"formats.":[125],"Together,":[126],"along":[127],"circuit":[131],"enhancements,":[132],"these":[133],"changes":[134],"than":[137],"40%":[138],"performance":[139],"improvement":[140],"over":[141],"Stratix\u00ae":[143],"10":[144],"family":[145],"FPGAs.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":26},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":13},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-05T08:41:31.759640","created_date":"2025-10-10T00:00:00"}