{"id":"https://openalex.org/W3008125474","doi":"https://doi.org/10.1145/3373087.3375303","title":"LUXOR","display_name":"LUXOR","publication_year":2020,"publication_date":"2020-02-23","ids":{"openalex":"https://openalex.org/W3008125474","doi":"https://doi.org/10.1145/3373087.3375303","mag":"3008125474"},"language":"en","primary_location":{"id":"doi:10.1145/3373087.3375303","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2003.03043","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Seyedramin Rasoulinezhad","orcid":null},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"Seyedramin Rasoulinezhad","raw_affiliation_strings":["The University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"The University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Siddhartha","orcid":null},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Siddhartha","raw_affiliation_strings":["The University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"The University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hao Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Zhou","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Lingli Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lingli Wang","raw_affiliation_strings":["Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"David Boland","orcid":null},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"David Boland","raw_affiliation_strings":["The University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"The University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"last","author":{"id":null,"display_name":"Philip H. W. Leong","orcid":null},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Philip H. W. Leong","raw_affiliation_strings":["The University of Sydney, Sydney, Australia"],"affiliations":[{"raw_affiliation_string":"The University of Sydney, Sydney, Australia","institution_ids":["https://openalex.org/I129604602"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I129604602"],"apc_list":null,"apc_paid":null,"fwci":13.9667,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.98392789,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"161","last_page":"171"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13308","display_name":"Cybernetics and Technology in Society","score":0.7192999720573425,"subfield":{"id":"https://openalex.org/subfields/1207","display_name":"History and Philosophy of Science"},"field":{"id":"https://openalex.org/fields/12","display_name":"Arts and Humanities"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},"topics":[{"id":"https://openalex.org/T13308","display_name":"Cybernetics and Technology in Society","score":0.7192999720573425,"subfield":{"id":"https://openalex.org/subfields/1207","display_name":"History and Philosophy of Science"},"field":{"id":"https://openalex.org/fields/12","display_name":"Arts and Humanities"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}},{"id":"https://openalex.org/T10481","display_name":"Computer Graphics and Visualization Techniques","score":0.6586999893188477,"subfield":{"id":"https://openalex.org/subfields/1704","display_name":"Computer Graphics and Computer-Aided Design"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5648000240325928},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5491999983787537},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5386999845504761},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5357999801635742},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5249000191688538},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5146999955177307},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4950999915599823},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4878000020980835}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6207000017166138},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5648000240325928},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5491999983787537},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5386999845504761},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5357999801635742},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5249000191688538},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5146999955177307},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4950999915599823},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4878000020980835},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.45509999990463257},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4377000033855438},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.4203000068664551},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.4187999963760376},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41749998927116394},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40880000591278076},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3953999876976013},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.3930000066757202},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3222000002861023},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.3027999997138977},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.29989999532699585},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.2874000072479248},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.2793999910354614},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.27639999985694885},{"id":"https://openalex.org/C134765980","wikidata":"https://www.wikidata.org/wiki/Q879126","display_name":"Bitwise operation","level":2,"score":0.26179999113082886},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25929999351501465},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25049999356269836}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3373087.3375303","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3373087.3375303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2003.03043","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2003.03043","pdf_url":"https://arxiv.org/pdf/2003.03043","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2003.03043","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2003.03043","pdf_url":"https://arxiv.org/pdf/2003.03043","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1983849809","https://openalex.org/W2076793873","https://openalex.org/W2102500637","https://openalex.org/W2110452354","https://openalex.org/W2120474114","https://openalex.org/W2123358761","https://openalex.org/W2126779549","https://openalex.org/W2127832194","https://openalex.org/W2128027813","https://openalex.org/W2154098113","https://openalex.org/W2160331356","https://openalex.org/W2293347572","https://openalex.org/W2300242332","https://openalex.org/W2585560244","https://openalex.org/W2761398658","https://openalex.org/W2765235648","https://openalex.org/W2785117529","https://openalex.org/W2891946740","https://openalex.org/W2916778556","https://openalex.org/W2949275038","https://openalex.org/W2951479717"],"related_works":[],"abstract_inverted_index":{"We":[0,66,90,155],"propose":[1],"two":[2],"tiers":[3],"of":[4,15,47,72,164,174,184,196],"modifications":[5,74],"to":[6,11,43,62,75,84,192],"FPGA":[7],"logic":[8,33,113,167,187,204],"cell":[9,34],"architecture":[10,56],"deliver":[12,160],"a":[13,37,69,125,172],"variety":[14,173],"performance":[16],"and":[17,59,78,87,115,142,152],"utilization":[18,168],"benefits":[19],"with":[20,36,104,180],"only":[21],"minor":[22],"area":[23,134],"overheads.":[24],"In":[25],"the":[26,45,105,110,116,120,132,147,178,193,197],"irst":[27],"tier,":[28],"we":[29,60,82],"augment":[30],"existing":[31],"commercial":[32],"datapaths":[35],"6-input":[38],"XOR":[39],"gate":[40],"in":[41,166,186],"order":[42],"improve":[44],"expressiveness":[46],"each":[48],"element,":[49],"while":[50,146],"maintaining":[51],"backward":[52],"compatibility.":[53],"This":[54],"new":[55],"is":[57,101,129,136,190],"vendor-agnostic,":[58],"refer":[61,83],"it":[63,128],"as":[64,85],"LUXOR.":[65],"also":[67],"consider":[68],"secondary":[70],"tier":[71],"vendor-speciic":[73],"both":[76,109],"Xilinx":[77,117],"Intel":[79,111],"FPGAs,":[80],"which":[81,189],"X-LUXOR+":[86],"I-LUXOR+":[88],"respectively.":[89,154],"demonstrate":[91,156],"that":[92,131,157],"compressor":[93],"tree":[94],"synthesis":[95],"using":[96],"generalized":[97],"parallel":[98],"counters":[99],"(GPCs)":[100],"further":[102],"improved":[103],"proposed":[106,202],"modifications.":[107],"Using":[108],"adaptive":[112],"module":[114],"slice":[118],"at":[119],"65nm":[121],"technology":[122],"node":[123],"for":[124,140,144],"comparative":[126],"study,":[127],"shown":[130],"silicon":[133],"overhead":[135],"less":[137],"than":[138],"0.5%":[139],"LUXOR":[141,158],"5-6%":[143],"LUXOR+,":[145],"delay":[148],"increments":[149],"are":[150],"1-6%":[151],"3-9%":[153],"can":[159],"an":[161,181],"average":[162,182],"reduction":[163,183],"13-19%":[165],"on":[169,200],"micro-benchmarks":[170],"from":[171],"domains.BNN":[175],"benchmarks":[176],"benefit":[177],"most":[179],"37-47%":[185],"utilization,":[188],"due":[191],"highly-efficient":[194],"mapping":[195],"XnorPopcount":[198],"operation":[199],"our":[201],"LUXOR+":[203],"cells.":[205]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2020-03-06T00:00:00"}