{"id":"https://openalex.org/W3031421781","doi":"https://doi.org/10.1145/3372799.3394367","title":"CITTA","display_name":"CITTA","publication_year":2020,"publication_date":"2020-05-29","ids":{"openalex":"https://openalex.org/W3031421781","doi":"https://doi.org/10.1145/3372799.3394367","mag":"3031421781"},"language":"en","primary_location":{"id":"doi:10.1145/3372799.3394367","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372799.3394367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://handle.uba.uva.nl/personal/pure/en/publications/citta-cache-interferenceaware-task-partitioning-for-realtime-multicore-systems(81ba3fd3-2d7a-47b2-b06a-4484067fcd54).html","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042902974","display_name":"Jun Xiao","orcid":"https://orcid.org/0000-0001-9306-3876"},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]},{"id":"https://openalex.org/I4210135670","display_name":"Amsterdam University of the Arts","ror":"https://ror.org/04dde1554","country_code":"NL","type":"education","lineage":["https://openalex.org/I4210135670"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Jun Xiao","raw_affiliation_strings":["University of Amsterdam, Amsterdam, Netherlands"],"affiliations":[{"raw_affiliation_string":"University of Amsterdam, Amsterdam, Netherlands","institution_ids":["https://openalex.org/I4210135670","https://openalex.org/I887064364"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084046597","display_name":"Andy D. Pimentel","orcid":"https://orcid.org/0000-0002-2043-4469"},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]},{"id":"https://openalex.org/I4210135670","display_name":"Amsterdam University of the Arts","ror":"https://ror.org/04dde1554","country_code":"NL","type":"education","lineage":["https://openalex.org/I4210135670"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Andy D. Pimentel","raw_affiliation_strings":["University of Amsterdam, Amsterdam, Netherlands"],"affiliations":[{"raw_affiliation_string":"University of Amsterdam, Amsterdam, Netherlands","institution_ids":["https://openalex.org/I4210135670","https://openalex.org/I887064364"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5042902974"],"corresponding_institution_ids":["https://openalex.org/I4210135670","https://openalex.org/I887064364"],"apc_list":null,"apc_paid":null,"fwci":0.7026,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66728202,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"97","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9905999898910522,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8635554313659668},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6260011792182922},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5970516204833984},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5700971484184265},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5597829222679138},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5268810391426086},{"id":"https://openalex.org/keywords/earliest-deadline-first-scheduling","display_name":"Earliest deadline first scheduling","score":0.4351904094219208},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.4212776720523834},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.4030901789665222},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.22984248399734497},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1946696639060974},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12470641732215881},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.10345837473869324},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.10168704390525818}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8635554313659668},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6260011792182922},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5970516204833984},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5700971484184265},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5597829222679138},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5268810391426086},{"id":"https://openalex.org/C32310161","wikidata":"https://www.wikidata.org/wiki/Q666365","display_name":"Earliest deadline first scheduling","level":5,"score":0.4351904094219208},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.4212776720523834},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.4030901789665222},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.22984248399734497},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1946696639060974},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12470641732215881},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.10345837473869324},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.10168704390525818},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1145/3372799.3394367","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372799.3394367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:dare.uva.nl:openaire_cris_publications/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","is_oa":true,"landing_page_url":"https://handle.uba.uva.nl/personal/pure/en/publications/citta-cache-interferenceaware-task-partitioning-for-realtime-multicore-systems(81ba3fd3-2d7a-47b2-b06a-4484067fcd54).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Xiao, J & Pimentel, A D 2020, CITTA: Cache Interference-Aware Task Partitioning for Real-Time Multi-core Systems. in LCTES '20 : the 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems : June 16, 2020, London, United Kingdom. New York, NY, pp. 97-107, 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2020, London, United Kingdom, 16/06/20. https://doi.org/10.1145/3372799.3394367","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:dare.uva.nl:publications/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","is_oa":true,"landing_page_url":"https://hdl.handle.net/11245.1/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","pdf_url":"https://pure.uva.nl/ws/files/54844166/3372799.3394367.pdf","source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Xiao, J & Pimentel, A D 2020, CITTA: Cache Interference-Aware Task Partitioning for Real-Time Multi-core Systems. in LCTES '20 : the 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems : June 16, 2020, London, United Kingdom. New York, NY, pp. 97-107, 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2020, London, United Kingdom, 16/06/20. https://doi.org/10.1145/3372799.3394367","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:uvapub:oai:dare.uva.nl:publications/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","is_oa":true,"landing_page_url":"https://dare.uva.nl/personal/pure/en/publications/citta-cache-interferenceaware-task-partitioning-for-realtime-multicore-systems(81ba3fd3-2d7a-47b2-b06a-4484067fcd54).html","pdf_url":"https://dare.uva.nl/personal/pure/en/publications/citta-cache-interferenceaware-task-partitioning-for-realtime-multicore-systems(81ba3fd3-2d7a-47b2-b06a-4484067fcd54).html","source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"LCTES '20: the 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems : June 16, 2020, London, United Kingdom, 97 - 107","raw_type":"info:eu-repo/semantics/conferencepaper"},{"id":"pmh:oai:dare.uva.nl:publications/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","is_oa":false,"landing_page_url":"http://hdl.handle.net/11245.1/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"pmh:oai:dare.uva.nl:openaire_cris_publications/81ba3fd3-2d7a-47b2-b06a-4484067fcd54","is_oa":true,"landing_page_url":"https://handle.uba.uva.nl/personal/pure/en/publications/citta-cache-interferenceaware-task-partitioning-for-realtime-multicore-systems(81ba3fd3-2d7a-47b2-b06a-4484067fcd54).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Xiao, J & Pimentel, A D 2020, CITTA: Cache Interference-Aware Task Partitioning for Real-Time Multi-core Systems. in LCTES '20 : the 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems : June 16, 2020, London, United Kingdom. New York, NY, pp. 97-107, 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2020, London, United Kingdom, 16/06/20. https://doi.org/10.1145/3372799.3394367","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/17","display_name":"Partnerships for the goals"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1968005108","https://openalex.org/W1987752344","https://openalex.org/W2019745154","https://openalex.org/W2038611612","https://openalex.org/W2050474377","https://openalex.org/W2076285066","https://openalex.org/W2102465293","https://openalex.org/W2115078506","https://openalex.org/W2115392544","https://openalex.org/W2135522804","https://openalex.org/W2141973605","https://openalex.org/W2148522570","https://openalex.org/W2163283745","https://openalex.org/W2171774238","https://openalex.org/W2343071281","https://openalex.org/W2908254926","https://openalex.org/W3008082241","https://openalex.org/W4230340736","https://openalex.org/W4233985188","https://openalex.org/W4249660747"],"related_works":["https://openalex.org/W2374555443","https://openalex.org/W2393789493","https://openalex.org/W2367142822","https://openalex.org/W2352790745","https://openalex.org/W2060984508","https://openalex.org/W2182592860","https://openalex.org/W2076947091","https://openalex.org/W1552447518","https://openalex.org/W2383668729","https://openalex.org/W4300092030"],"abstract_inverted_index":{"Shared":[0],"caches":[1],"in":[2,8,26,56,140],"multi-core":[3,42],"processors":[4],"introduce":[5],"serious":[6],"difficulties":[7],"providing":[9],"guarantees":[10],"on":[11,86],"the":[12,20,23,27,34,57,83,117],"real-time":[13,41],"properties":[14],"of":[15,37,59,102,111,120,142],"embedded":[16],"software":[17],"due":[18],"to":[19,81,115],"interaction":[21],"and":[22,104],"resulting":[24],"contention":[25],"shared":[28,45,60],"caches.":[29,46],"Prior":[30],"work":[31],"has":[32],"studied":[33],"schedulability":[35,100,118],"analysis":[36,101],"global":[38,123,137],"scheduling":[39,52,55,125,139],"for":[40],"systems":[43],"with":[44],"This":[47],"paper":[48],"considers":[49],"another":[50],"common":[51],"paradigm:":[53],"partitioned":[54],"presence":[58],"cache":[61,87],"interference.":[62],"To":[63],"achieve":[64],"this,":[65],"we":[66],"propose":[67],"CITTA,":[68],"a":[69,91],"cache-interference":[70],"aware":[71],"task":[72,143],"partitioning":[73],"algorithm.":[74],"An":[75],"integer":[76],"programming":[77],"formulation":[78],"is":[79,94,113],"constructed":[80],"calculate":[82],"upper":[84],"bound":[85],"interference":[88],"exhibited":[89],"by":[90,96],"task,":[92],"which":[93],"required":[95],"CITTA.":[97],"We":[98],"conduct":[99],"CITTA":[103,121,135],"formally":[105],"prove":[106],"its":[107],"correctness.":[108],"A":[109],"set":[110],"experiments":[112],"performed":[114],"evaluate":[116],"performance":[119],"against":[122],"EDF":[124,138],"over":[126],"randomly":[127],"generated":[128],"tasksets.":[129],"Our":[130],"empirical":[131],"evaluations":[132],"show":[133],"that":[134],"outperforms":[136],"terms":[141],"sets":[144],"deemed":[145],"schedulable.":[146]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2020-06-05T00:00:00"}
