{"id":"https://openalex.org/W3012035221","doi":"https://doi.org/10.1145/3372780.3378167","title":"Physical Design for 3D Chiplets and System Integration","display_name":"Physical Design for 3D Chiplets and System Integration","publication_year":2020,"publication_date":"2020-03-20","ids":{"openalex":"https://openalex.org/W3012035221","doi":"https://doi.org/10.1145/3372780.3378167","mag":"3012035221"},"language":"en","primary_location":{"id":"doi:10.1145/3372780.3378167","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372780.3378167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041821882","display_name":"Cliff Hou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Cliff Hou","raw_affiliation_strings":["TSMC, Hsinchu, Taiwan Roc"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TSMC, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I4210120917"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5041821882"],"corresponding_institution_ids":["https://openalex.org/I4210120917"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10783","display_name":"Additive Manufacturing and 3D Printing Technologies","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2203","display_name":"Automotive Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9768000245094299,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.6247774362564087},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5881639719009399},{"id":"https://openalex.org/keywords/system-integration","display_name":"System integration","score":0.5841631889343262},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47086063027381897},{"id":"https://openalex.org/keywords/integrated-design","display_name":"Integrated design","score":0.43746018409729004},{"id":"https://openalex.org/keywords/wafer-level-packaging","display_name":"Wafer-level packaging","score":0.43699318170547485},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43323713541030884},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.42165184020996094},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.41895806789398193},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.40557587146759033},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3374847173690796},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25560468435287476},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14697372913360596},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13317707180976868},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1286439299583435},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1122104823589325}],"concepts":[{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.6247774362564087},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5881639719009399},{"id":"https://openalex.org/C19527686","wikidata":"https://www.wikidata.org/wiki/Q1665453","display_name":"System integration","level":2,"score":0.5841631889343262},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47086063027381897},{"id":"https://openalex.org/C2778588580","wikidata":"https://www.wikidata.org/wiki/Q6043060","display_name":"Integrated design","level":2,"score":0.43746018409729004},{"id":"https://openalex.org/C2780288131","wikidata":"https://www.wikidata.org/wiki/Q4017648","display_name":"Wafer-level packaging","level":3,"score":0.43699318170547485},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43323713541030884},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.42165184020996094},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.41895806789398193},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.40557587146759033},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3374847173690796},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25560468435287476},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14697372913360596},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13317707180976868},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1286439299583435},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1122104823589325},{"id":"https://openalex.org/C147176958","wikidata":"https://www.wikidata.org/wiki/Q77590","display_name":"Civil engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3372780.3378167","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372780.3378167","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6700000166893005,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3047088815","https://openalex.org/W3033866926","https://openalex.org/W2783427658","https://openalex.org/W2088052449","https://openalex.org/W2128696525","https://openalex.org/W4252443929","https://openalex.org/W3136387861","https://openalex.org/W146048418","https://openalex.org/W3172718840","https://openalex.org/W4200290232"],"abstract_inverted_index":{"The":[0,218,243],"convergence":[1],"of":[2,124,330,409,411],"5G":[3,45],"and":[4,30,46,55,61,96,110,131,147,152,162,170,182,191,199,207,215,225,240,261,275,282,293,307,309,317,332,395,404,429,433],"Artificial":[5],"Intelligence":[6],"(AI)":[7],"that":[8,75,103],"covers":[9,248],"the":[10,41,174,230,259,386],"gamut":[11],"from":[12,70,353,370,424,436],"cloud":[13],"data":[14,189],"centers":[15],"through":[16,138],"network":[17],"routers":[18],"to":[19,24,72,99,187,237,271,348,355,372,380],"edge":[20],"applications":[21],"is":[22,68,235,375],"poised":[23],"open":[25],"possibilities":[26],"beyond":[27],"our":[28,37],"imagination":[29],"transform":[31],"how":[32],"we":[33],"will":[34,279],"go":[35],"about":[36],"daily":[38],"lives.":[39],"As":[40],"foundational":[42],"technology":[43],"supporting":[44],"AI":[47],"innovation,":[48,228],"semiconductors":[49],"strive":[50],"for":[51,116,141,150,178,196,290,385],"greater":[52],"system":[53,79,101,117,241,294,305,318],"performance":[54],"broader":[56],"bandwidth,":[57],"while":[58],"increasing":[59],"functionality":[60],"lowering":[62],"cost.":[63],"In":[64],"response,":[65],"device":[66],"innovation":[67],"transitioning":[69],"SoCs":[71],"3D":[73,108,179,213,238,268,291,301,315],"chiplets":[74,109,239,292,316],"combine":[76],"advanced":[77],"wafer-level":[78,115],"integration":[80,102,118,149],"(WLSI)":[81],"technologies":[82],"such":[83],"as":[84,406],"CoWoS\u00ae":[85],"(Chip":[86],"on":[87,89,114],"Wafer":[88],"Substrate),":[90],"Integrated":[91],"Fan-Out":[92],"(InFO),":[93],"Wafer-on-Wafer":[94],"(WoW)":[95],"System-on-Integrated-Chips":[97],"(SoIC),":[98],"enable":[100],"meets":[104],"these":[105,281],"demands.":[106],"Designing":[107],"housing":[111],"various":[112],"chips":[113],"creates":[119],"a":[120,407],"whole":[121],"new":[122,155],"set":[123],"challenges.":[125],"These":[126],"start":[127,257],"with":[128,193],"design":[129,140,181,185,205,264,288],"partitioning":[130],"include":[132],"handling":[133],"interfaces":[134],"between":[135],"or":[136],"passing":[137],"chips,":[139],"testing":[142],"(DFT),":[143],"thermal":[144,226,245,249,253,320],"dissipation,":[145],"databases":[146],"tools":[148,192],"chip":[151,263],"packaging":[153,194,311],"design,":[154,270,300,314],"IO/ESD":[156],"(electrostatic":[157],"discharge),":[158],"simulation":[159],"run":[160],"time":[161],"tool":[163],"capacity,":[164],"among":[165],"others.":[166],"Considering":[167],"current":[168,244],"capabilities":[169],"constraints,":[171,308],"divide-and-conquer":[172],"remains":[173],"most":[175],"feasible":[176],"approach":[177],"chiplet":[180],"packaging.":[183],"Chiplet":[184],"needs":[186,222],"integrate":[188],"bases":[190],"environments":[195],"both":[197],"verification":[198,214],"optimization.":[200],"Leveraging":[201],"existing":[202],"2D":[203],"physical":[204,287],"solutions":[206,289,384],"chip-level":[208],"abstraction":[209],"can":[210],"help":[211],"meet":[212],"optimization":[216,234,321],"requirements.":[217],"IC":[219,269],"industry":[220],"also":[221,363],"more":[223],"DFT":[224],"dissipation":[227],"especially":[229],"latter":[231],"one.":[232],"Thermal":[233],"critical":[236],"integration.":[242,295],"solution":[246],"only":[247],"analysis":[250],"+":[251],"system-level":[252],"dissipation.":[254],"It":[255],"should":[256],"at":[258,334,359],"IPs":[260],"across":[262],"process,":[265],"i.e.,":[266],"thermal-aware":[267],"cover":[272],"IP,":[273],"macros,":[274],"transistors.":[276],"This":[277],"speech":[278],"address":[280],"other":[283],"challenges,":[284],"then":[285],"propose":[286],"CCS":[296],"CONCEPTS":[297],"-":[298],"VLSI":[299,304,310],"integrated":[302],"circuits,":[303],"specification":[306],"KEYWORDS":[312],"Physical":[313],"integration,":[319],"BIOGRAPHY":[322],"Dr.":[323,361,398],"Cliff":[324],"Hou":[325,362,399],"was":[326],"appointed":[327],"Vice":[328],"President":[329],"Research":[331],"Development":[333],"Taiwan":[335],"Semiconductor":[336],"Manufacturing":[337],"Co.":[338],"Ltd.":[339],"(TSMC)":[340],"in":[341,391,413,421,431],"2011.":[342],"Since":[343],"1999,":[344],"he":[345],"has":[346],"worked":[347],"establish":[349],"node-specific":[350],"reference":[351],"flows":[352],"0.13\u03bcm":[354],"today's":[356],"leading-edge":[357],"3nm":[358],"TSMC.":[360],"led":[364],"TSMC's":[365,378],"in-house":[366],"IP":[367],"development":[368],"teams":[369],"2008":[371],"2010.":[373],"He":[374,417],"now":[376],"spearheading":[377],"efforts":[379],"build":[381],"total":[382],"platform":[383],"industry's":[387],"high":[388],"growth":[389],"markets":[390],"Mobile,":[392],"IoT,":[393],"Automotive,":[394],"High-Performance":[396],"Computing.":[397],"holds":[400],"44":[401],"U.S.":[402],"Patents":[403],"serves":[405],"member":[408],"Board":[410],"Directors":[412],"Global":[414],"Unichip":[415],"Corp.":[416],"received":[418],"B.S.":[419],"degree":[420],"Control":[422],"Engineering":[423,435],"Taiwan's":[425],"National":[426],"Chiao-Tung":[427],"University,":[428],"Ph.D.":[430],"Electrical":[432],"Computer":[434],"Syracuse":[437],"University.":[438]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
