{"id":"https://openalex.org/W3012165124","doi":"https://doi.org/10.1145/3372780.3375564","title":"Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV","display_name":"Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV","publication_year":2020,"publication_date":"2020-03-20","ids":{"openalex":"https://openalex.org/W3012165124","doi":"https://doi.org/10.1145/3372780.3375564","mag":"3012165124"},"language":"en","primary_location":{"id":"doi:10.1145/3372780.3375564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372780.3375564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019298173","display_name":"Dimitrios Mangiras","orcid":"https://orcid.org/0000-0002-3602-5862"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Dimitrios Mangiras","raw_affiliation_strings":["Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067917827","display_name":"Pavlos M. Mattheakis","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138743","display_name":"Siemens (France)","ror":"https://ror.org/04q9w3z30","country_code":"FR","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210138743"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pavlos Mattheakis","raw_affiliation_strings":["Mentor, a Siemens Business, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Mentor, a Siemens Business, Grenoble, France","institution_ids":["https://openalex.org/I4210138743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073743453","display_name":"Pierre-Olivier Ribet","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138743","display_name":"Siemens (France)","ror":"https://ror.org/04q9w3z30","country_code":"FR","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210138743"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pierre-Olivier Ribet","raw_affiliation_strings":["Mentor, a Siemens Business, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Mentor, a Siemens Business, Grenoble, France","institution_ids":["https://openalex.org/I4210138743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074704256","display_name":"Giorgos Dimitrakopoulos","orcid":"https://orcid.org/0000-0003-3688-7865"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Giorgos Dimitrakopoulos","raw_affiliation_strings":["Democritus University of Thrace, Xanthi, Greece"],"affiliations":[{"raw_affiliation_string":"Democritus University of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5019298173"],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.02108525,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"25","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.7732977867126465},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6403042674064636},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6224544048309326},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6034405827522278},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.530000627040863},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.49011000990867615},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4652218818664551},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.45014527440071106},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4485902190208435},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4484163522720337},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.4481467604637146},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.444868803024292},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.43436872959136963},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34109795093536377},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3216826319694519},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.283562034368515},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2751784026622772},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10015511512756348},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08464112877845764},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06350558996200562},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.06199565529823303}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.7732977867126465},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6403042674064636},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6224544048309326},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6034405827522278},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.530000627040863},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.49011000990867615},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4652218818664551},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.45014527440071106},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4485902190208435},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4484163522720337},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.4481467604637146},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.444868803024292},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.43436872959136963},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34109795093536377},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3216826319694519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.283562034368515},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2751784026622772},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10015511512756348},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08464112877845764},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06350558996200562},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.06199565529823303},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3372780.3375564","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3372780.3375564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2020 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W658677875","https://openalex.org/W1981555216","https://openalex.org/W1982199193","https://openalex.org/W2007510972","https://openalex.org/W2011430131","https://openalex.org/W2011631589","https://openalex.org/W2012786899","https://openalex.org/W2025640338","https://openalex.org/W2063006063","https://openalex.org/W2069142841","https://openalex.org/W2108050730","https://openalex.org/W2113682107","https://openalex.org/W2131074607","https://openalex.org/W2146141391","https://openalex.org/W2150499679","https://openalex.org/W2404274178","https://openalex.org/W2535521862","https://openalex.org/W2607848558","https://openalex.org/W2626946404","https://openalex.org/W2840197104","https://openalex.org/W2955479062","https://openalex.org/W4236699753"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766","https://openalex.org/W3006003651","https://openalex.org/W2617666058","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2384600254"],"abstract_inverted_index":{"On-Chip":[0],"Variation":[1],"(OCV)":[2],"in":[3,56,139,143],"advanced":[4],"technology":[5],"nodes":[6],"introduces":[7],"delay":[8],"uncertainties":[9],"that":[10,91],"may":[11],"cause":[12],"timing":[13],"violations.":[14],"This":[15,130],"problem":[16],"drastically":[17],"affects":[18],"the":[19,24,35,41,44,50,53,63,81,95,123,127,136],"clock":[20,54,64,70,75,82,96,102,128,144],"tree":[21,65,76,97],"that,":[22],"besides":[23],"growing":[25],"design":[26],"complexity,":[27],"needs":[28],"to":[29,33,60,68,94,117,121,150],"be":[30],"appropriately":[31],"synthesized":[32],"tackle":[34],"increased":[36,73],"variability":[37],"effects.":[38],"To":[39],"reduce":[40],"magnitude":[42],"of":[43,80,126],"clock-induced":[45],"OCV,":[46],"we":[47],"incrementally":[48,108],"relocate":[49],"flip-flops":[51],"and":[52,107,115],"gaters":[55],"a":[57,87],"bottom-up":[58],"manner":[59],"implicitly":[61],"guide":[62],"synthesis":[66,98],"engine":[67],"produce":[69],"trees":[71,145],"with":[72],"common":[74,124],"paths.":[77],"The":[78,101],"relocation":[79],"elements":[83,103],"is":[84,92,132],"performed":[85],"using":[86],"soft":[88],"clustering":[89],"approach":[90],"orthogonal":[93],"method":[99,138],"used.":[100],"are":[104,147],"repeatedly":[105],"relocated":[106],"re-clustered,":[109],"thus":[110],"gradually":[111],"forming":[112],"better":[113],"clusters":[114],"settling":[116],"more":[118,148],"appropriate":[119],"positions":[120],"increase":[122],"paths":[125],"tree.":[129],"behavior":[131],"verified":[133],"by":[134],"applying":[135],"proposed":[137],"industrial":[140],"designs,":[141],"resulting":[142],"which":[146],"resilient":[149],"process":[151],"variations,":[152],"while":[153],"exhibiting":[154],"improved":[155],"overall":[156],"timing.":[157]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}