{"id":"https://openalex.org/W2979772872","doi":"https://doi.org/10.1145/3359986.3361199","title":"Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog","display_name":"Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog","publication_year":2019,"publication_date":"2019-10-07","ids":{"openalex":"https://openalex.org/W2979772872","doi":"https://doi.org/10.1145/3359986.3361199","mag":"2979772872"},"language":"en","primary_location":{"id":"doi:10.1145/3359986.3361199","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3359986.3361199","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.repository.cam.ac.uk/handle/1810/299944","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110244397","display_name":"David Greaves","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"David J. Greaves","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5110244397"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8303574323654175},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7768319845199585},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6226654648780823},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.5689631700515747},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5276321768760681},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.44289180636405945},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.4152142107486725},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3932145833969116},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3689228892326355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3371438682079315},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21674811840057373}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8303574323654175},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7768319845199585},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6226654648780823},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.5689631700515747},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5276321768760681},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.44289180636405945},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.4152142107486725},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3932145833969116},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3689228892326355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3371438682079315},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21674811840057373}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3359986.3361199","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3359986.3361199","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design","raw_type":"proceedings-article"},{"id":"pmh:oai:www.repository.cam.ac.uk:1810/299944","is_oa":true,"landing_page_url":"https://www.repository.cam.ac.uk/handle/1810/299944","pdf_url":"https://www.repository.cam.ac.uk/handle/1810/299944","source":{"id":"https://openalex.org/S4306401777","display_name":"Apollo (University of Cambridge)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I241749","host_organization_name":"University of Cambridge","host_organization_lineage":["https://openalex.org/I241749"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Object"},{"id":"doi:10.17863/cam.47013","is_oa":true,"landing_page_url":"https://doi.org/10.17863/cam.47013","pdf_url":null,"source":{"id":"https://openalex.org/S7407050737","display_name":"Apollo","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Other"}],"best_oa_location":{"id":"pmh:oai:www.repository.cam.ac.uk:1810/299944","is_oa":true,"landing_page_url":"https://www.repository.cam.ac.uk/handle/1810/299944","pdf_url":"https://www.repository.cam.ac.uk/handle/1810/299944","source":{"id":"https://openalex.org/S4306401777","display_name":"Apollo (University of Cambridge)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I241749","host_organization_name":"University of Cambridge","host_organization_lineage":["https://openalex.org/I241749"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Object"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2979772872.pdf","grobid_xml":"https://content.openalex.org/works/W2979772872.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W2030220202","https://openalex.org/W2049600101","https://openalex.org/W2116704858","https://openalex.org/W2123146353","https://openalex.org/W2128767383","https://openalex.org/W2148593819","https://openalex.org/W2153337316","https://openalex.org/W2296514843","https://openalex.org/W3098156094","https://openalex.org/W4211007335","https://openalex.org/W4229487452","https://openalex.org/W4233718422"],"related_works":["https://openalex.org/W1601646354","https://openalex.org/W2086733238","https://openalex.org/W2078700326","https://openalex.org/W1482645738","https://openalex.org/W4386159909","https://openalex.org/W4233602124","https://openalex.org/W3098156094","https://openalex.org/W2156965212","https://openalex.org/W2948321003","https://openalex.org/W2755110126"],"abstract_inverted_index":{"Bluespec":[0,22,101,137],"[13]":[1],"is":[2,10],"a":[3,24,36,148],"hardware":[4,31,83],"description":[5],"language":[6],"where":[7],"all":[8],"behaviour":[9],"expressed":[11],"in":[12,50,99,110],"rules":[13,74,169,176],"that":[14],"execute":[15],"atomically.":[16],"The":[17],"standard":[18,56,100,174],"compilation":[19,175],"semantics":[20,135],"for":[21,159],"enforce":[23],"particular":[25],"mapping":[26],"between":[27,73],"rule":[28,49],"firing":[29,44],"and":[30,89,122,154,177],"clock":[32,52,142,152],"cycles,":[33,143],"such":[34,64,85,102,112],"as":[35,65,86,113,170],"register":[37,149],"only":[38],"being":[39],"updated":[40],"by":[41],"exactly":[42],"one":[43,48,151],"of":[45,136,157,172],"at":[46],"most":[47],"any":[51,61],"cycle.":[53],"Also,":[54],"the":[55,78,133,165],"compiler":[57],"does":[58],"not":[59],"introduce":[60],"additional":[62],"state,":[63],"credit-based":[66],"or":[67,115],"round-robin":[68],"arbiters":[69,158],"to":[70,119,138,147],"guarantee":[71],"fairness":[72],"over":[75],"time.":[76],"On":[77],"other":[79],"hand,":[80],"many":[81],"useful":[82],"resources,":[84],"complex":[87],"ALUs":[88],"synchronous":[90],"RAMs,":[91],"are":[92,126],"pipelined.":[93],"Unlike":[94],"typical":[95],"high-level":[96],"synthesis":[97],"tools,":[98],"resources":[103],"cannot":[104],"be":[105],"invoked":[106],"using":[107],"infix":[108],"operators":[109],"expressions":[111],"A[e]":[114],"e1*e2":[116],"since":[117],"binding":[118],"specific":[120],"instances":[121],"multi-clock":[123,160],"cycle":[124,153,161],"schedules":[125],"required.":[127],"In":[128],"this":[129],"paper":[130],"we":[131,178],"extend":[132],"reference":[134],"decouple":[139],"it":[140],"from":[141,182],"allowing":[144],"multiple":[145],"updates":[146],"within":[150],"automatic":[155],"instantiation":[156],"behaviour.":[162],"We":[163],"describe":[164],"new":[166],"semantic":[167],"packing":[168],"extensions":[171],"our":[173],"report":[179],"early":[180],"results":[181],"an":[183],"open-source,":[184],"fully-functional":[185],"implementation.":[186]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
