{"id":"https://openalex.org/W2985330652","doi":"https://doi.org/10.1145/3357526.3357538","title":"Endurance enhancement of write-optimized STT-RAM caches","display_name":"Endurance enhancement of write-optimized STT-RAM caches","publication_year":2019,"publication_date":"2019-09-30","ids":{"openalex":"https://openalex.org/W2985330652","doi":"https://doi.org/10.1145/3357526.3357538","mag":"2985330652"},"language":"en","primary_location":{"id":"doi:10.1145/3357526.3357538","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3357526.3357538","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064250139","display_name":"Puneet Saraf","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Puneet Saraf","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, Tamil Nadu, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, Tamil Nadu, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001143341","display_name":"Madhu Mutyam","orcid":"https://orcid.org/0000-0003-1638-4195"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Madhu Mutyam","raw_affiliation_strings":["Indian Institute of Technology Madras, Chennai, Tamil Nadu, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Madras, Chennai, Tamil Nadu, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24676775"],"apc_list":null,"apc_paid":null,"fwci":0.8628,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.69804121,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"101","last_page":"113"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.801598072052002},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7991992235183716},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7223635315895081},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6412519216537476},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5608437061309814},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5363845229148865},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.53304523229599},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5229492783546448},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5197322368621826},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.46518367528915405},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4604007303714752},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28522011637687683},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23166415095329285}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.801598072052002},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7991992235183716},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7223635315895081},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6412519216537476},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5608437061309814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5363845229148865},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.53304523229599},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5229492783546448},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5197322368621826},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.46518367528915405},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4604007303714752},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28522011637687683},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23166415095329285},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3357526.3357538","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3357526.3357538","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1549725729","https://openalex.org/W1955235267","https://openalex.org/W1963958751","https://openalex.org/W1984574424","https://openalex.org/W1991342601","https://openalex.org/W2015477844","https://openalex.org/W2036853599","https://openalex.org/W2047379549","https://openalex.org/W2064977311","https://openalex.org/W2090994050","https://openalex.org/W2108048675","https://openalex.org/W2116826022","https://openalex.org/W2125428294","https://openalex.org/W2127419525","https://openalex.org/W2143773524","https://openalex.org/W2147657366","https://openalex.org/W2155366133","https://openalex.org/W2155551886","https://openalex.org/W2270110274","https://openalex.org/W2536491920","https://openalex.org/W2588003476","https://openalex.org/W2725159389","https://openalex.org/W2763915470","https://openalex.org/W4237478817","https://openalex.org/W4237860043","https://openalex.org/W4245987560","https://openalex.org/W4247189428"],"related_works":["https://openalex.org/W2110321764","https://openalex.org/W2783549708","https://openalex.org/W2036350002","https://openalex.org/W1909296377","https://openalex.org/W2023834321","https://openalex.org/W2089002058","https://openalex.org/W2104937488","https://openalex.org/W3185029353","https://openalex.org/W2810613542","https://openalex.org/W1744689038"],"abstract_inverted_index":{"Low":[0],"density":[1],"and":[2,41,62,112,171,191],"high":[3,39,59],"leakage":[4],"power":[5],"of":[6,55,107,116,121,125,164,173,187],"SRAM":[7,30,74],"are":[8,46,143,147],"the":[9,32,76,85,104,113,139,150,161,165,183,217],"major":[10],"setbacks":[11],"for":[12,29,49,189,193],"its":[13],"scalability.":[14],"Non-volatile":[15],"memory":[16,23],"(NVM)":[17],"like":[18],"spin-transfer":[19],"torque":[20],"random":[21],"access":[22],"(STT-RAM)":[24],"is":[25,212],"a":[26,129,213],"suitable":[27],"replacement":[28,136],"at":[31,75],"last":[33],"level":[34],"cache":[35,135,140,153,166],"(LLC).":[36],"NVM":[37],"offers":[38],"density,":[40],"near":[42],"zero":[43],"leakage,":[44],"which":[45],"highly":[47],"desired":[48],"on-chip":[50],"caches.":[51],"A":[52],"few":[53],"drawbacks":[54],"STT-RAM":[56,174,197],"such":[57],"as":[58],"write":[60,86,110],"latency":[61,87],"limited":[63],"endurance,":[64],"have":[65,80],"to":[66,83,145,149,196],"be":[67],"taken":[68],"care":[69,120],"before":[70],"it":[71],"can":[72],"replace":[73],"LLC.":[77,175],"Prior":[78],"works":[79],"either":[81],"tried":[82],"optimize":[84],"or":[88],"endurance.":[89],"In":[90],"this":[91],"paper,":[92],"by":[93,102],"considering":[94],"write-optimized":[95,126],"STT-RAM,":[96],"we":[97,203],"propose":[98],"endurance":[99,172],"improvement":[100,186,215],"techniques":[101],"reducing":[103],"maximum":[105,184],"number":[106,115],"writes,":[108],"global":[109],"variation,":[111],"average":[114],"writes.":[117],"We":[118,132,176],"take":[119],"low":[122],"retention":[123],"time":[124],"STT-RAMs":[127],"using":[128],"refresh":[130],"mechanism.":[131],"employ":[133],"refresh-aware":[134,156,180,209],"policies":[137],"wherein":[138],"blocks":[141],"that":[142,178],"about":[144],"expire":[146],"preferred":[148],"recently":[151],"refreshed":[152],"blocks.":[154],"This":[155],"policy,":[157,210],"when":[158],"combined":[159],"with":[160,198,207],"recency":[162,205],"information":[163,206],"blocks,":[167],"enhances":[168],"both":[169],"performance":[170],"show":[177],"our":[179,208],"policy":[181],"achieves":[182],"lifetime":[185],"32.5%":[188],"single-core":[190],"70.7%":[192],"muti-core":[194],"compared":[195],"no":[199],"wear":[200],"leveling.":[201],"When":[202],"combine":[204],"there":[211],"slight":[214],"in":[216],"performance.":[218]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}