{"id":"https://openalex.org/W2986130717","doi":"https://doi.org/10.1145/3356045.3360720","title":"Asymmetric routing in 3D NoC using interleaved edge routers","display_name":"Asymmetric routing in 3D NoC using interleaved edge routers","publication_year":2019,"publication_date":"2019-10-13","ids":{"openalex":"https://openalex.org/W2986130717","doi":"https://doi.org/10.1145/3356045.3360720","mag":"2986130717"},"language":"en","primary_location":{"id":"doi:10.1145/3356045.3360720","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3356045.3360720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th International Workshop on Network on Chip Architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088732810","display_name":"Rose George Kunthara","orcid":"https://orcid.org/0000-0001-5376-5718"},"institutions":[{"id":"https://openalex.org/I20497027","display_name":"Cochin University of Science and Technology","ror":"https://ror.org/00a4kqq17","country_code":"IN","type":"education","lineage":["https://openalex.org/I20497027"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Rose George Kunthara","raw_affiliation_strings":["CUSAT, Cochin, India"],"affiliations":[{"raw_affiliation_string":"CUSAT, Cochin, India","institution_ids":["https://openalex.org/I20497027"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069049870","display_name":"Rekha K. James","orcid":"https://orcid.org/0000-0002-4149-1358"},"institutions":[{"id":"https://openalex.org/I20497027","display_name":"Cochin University of Science and Technology","ror":"https://ror.org/00a4kqq17","country_code":"IN","type":"education","lineage":["https://openalex.org/I20497027"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rekha K James","raw_affiliation_strings":["CUSAT, Cochin, India"],"affiliations":[{"raw_affiliation_string":"CUSAT, Cochin, India","institution_ids":["https://openalex.org/I20497027"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041804933","display_name":"Simi Zerine Sleeba","orcid":"https://orcid.org/0000-0002-2716-270X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Simi Zerine Sleeba","raw_affiliation_strings":["Viswajyothi College of Engineering and Technology, Muvattupuzha, India"],"affiliations":[{"raw_affiliation_string":"Viswajyothi College of Engineering and Technology, Muvattupuzha, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021641760","display_name":"John Jose","orcid":"https://orcid.org/0000-0002-0314-8778"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"John Jose","raw_affiliation_strings":["Indian Institute of Technology, Guwahati, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Guwahati, India","institution_ids":["https://openalex.org/I1317621060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5088732810"],"corresponding_institution_ids":["https://openalex.org/I20497027"],"apc_list":null,"apc_paid":null,"fwci":0.3537,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.64359038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10018","display_name":"Advancements in Battery Materials","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7761280536651611},{"id":"https://openalex.org/keywords/deflection-routing","display_name":"Deflection routing","score":0.6997864246368408},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6827220916748047},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6218246221542358},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6207486987113953},{"id":"https://openalex.org/keywords/virtual-channel","display_name":"Virtual channel","score":0.513200044631958},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.4945785701274872},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.45647791028022766},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.413802832365036},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.408808171749115},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40758877992630005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37707215547561646},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.34456491470336914},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.30432388186454773},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.15285053849220276},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.08288270235061646}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7761280536651611},{"id":"https://openalex.org/C2781404978","wikidata":"https://www.wikidata.org/wiki/Q5251653","display_name":"Deflection routing","level":5,"score":0.6997864246368408},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6827220916748047},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6218246221542358},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6207486987113953},{"id":"https://openalex.org/C2777076873","wikidata":"https://www.wikidata.org/wiki/Q2291875","display_name":"Virtual channel","level":3,"score":0.513200044631958},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.4945785701274872},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.45647791028022766},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.413802832365036},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.408808171749115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40758877992630005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37707215547561646},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.34456491470336914},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.30432388186454773},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.15285053849220276},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.08288270235061646},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3356045.3360720","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3356045.3360720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 12th International Workshop on Network on Chip Architectures","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1493914388","https://openalex.org/W1983099350","https://openalex.org/W2004148499","https://openalex.org/W2057649385","https://openalex.org/W2071003187","https://openalex.org/W2104674486","https://openalex.org/W2147657366","https://openalex.org/W2382505656","https://openalex.org/W2923625094","https://openalex.org/W3140261852","https://openalex.org/W4256175350","https://openalex.org/W6600708292"],"related_works":["https://openalex.org/W2013729863","https://openalex.org/W2138410650","https://openalex.org/W2293437742","https://openalex.org/W4212914479","https://openalex.org/W2181632526","https://openalex.org/W1986253853","https://openalex.org/W2439487276","https://openalex.org/W3159592544","https://openalex.org/W2052816277","https://openalex.org/W2560886726"],"abstract_inverted_index":{"Network":[0],"on":[1],"Chip":[2],"(NoC)":[3],"concept":[4],"has":[5,126],"evolved":[6],"as":[7],"a":[8,20],"standard":[9],"design":[10,125],"approach":[11,101],"for":[12,110],"integrating":[13],"large":[14],"number":[15,76,143],"of":[16,35,44,77,144],"processing":[17],"cores":[18],"within":[19],"single":[21],"die.":[22],"The":[23],"performance":[24],"improvements":[25],"which":[26,82],"occur":[27],"due":[28],"to":[29,87,137],"topological":[30],"optimizations":[31],"and":[32,61,90,133],"architectural":[33],"enhancements":[34],"NoCs":[36],"can":[37],"be":[38],"remarkably":[39],"increased":[40],"by":[41,58],"the":[42],"adoption":[43],"3D":[45,51,72,104],"IC":[46],"fabrication":[47],"technology.":[48],"However,":[49],"conventional":[50],"NoC":[52,73,105,112],"architecture":[53],"designs":[54],"are":[55],"significantly":[56],"affected":[57],"router":[59],"area":[60,84],"power":[62],"dissipation":[63],"issues":[64],"when":[65],"compared":[66,136],"with":[67],"traditional":[68],"2D":[69],"NoCs.":[70],"Also,":[71],"utilizes":[74],"considerable":[75],"Through":[78],"Silicon":[79],"Vias":[80],"(TSVs)":[81],"raises":[83],"overhead":[85],"leading":[86],"minimal":[88],"yield":[89],"wafer":[91],"utilization.":[92],"In":[93],"this":[94],"paper,":[95],"we":[96],"propose":[97],"an":[98],"asymmetric":[99],"routing":[100],"in":[102],"bufferless":[103,139],"using":[106],"interleaved":[107],"edge":[108],"routers":[109],"enhancing":[111],"performance.":[113],"Simulation":[114],"results":[115],"show":[116],"that":[117],"our":[118],"proposed":[119],"M-3D":[120],"(Modified":[121],"Three":[122],"Dimensional)":[123],"mesh":[124],"better":[127],"throughput,":[128],"lower":[129],"average":[130],"flit":[131],"latency":[132],"deflection":[134],"rate":[135],"state-of-the-art":[138],"networks,":[140],"employing":[141],"same":[142],"routers.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
