{"id":"https://openalex.org/W2989651171","doi":"https://doi.org/10.1145/3349567.3351730","title":"Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction","display_name":"Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction","publication_year":2019,"publication_date":"2019-10-13","ids":{"openalex":"https://openalex.org/W2989651171","doi":"https://doi.org/10.1145/3349567.3351730","mag":"2989651171"},"language":"en","primary_location":{"id":"doi:10.1145/3349567.3351730","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3349567.3351730","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3349567.3351730","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3349567.3351730","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032172523","display_name":"Ruben Vazquez","orcid":"https://orcid.org/0000-0002-6496-1498"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ruben Vazquez","raw_affiliation_strings":["University of Florida"],"affiliations":[{"raw_affiliation_string":"University of Florida","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102928781","display_name":"Ross Gordon","orcid":"https://orcid.org/0000-0003-1034-8695"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ann Gordon-Ross","raw_affiliation_strings":["University of Florida"],"affiliations":[{"raw_affiliation_string":"University of Florida","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088031457","display_name":"Greg Stitt","orcid":"https://orcid.org/0000-0001-7159-7439"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Stitt","raw_affiliation_strings":["University of Florida"],"affiliations":[{"raw_affiliation_string":"University of Florida","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5032172523"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.51787112,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8859231472015381},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7672461271286011},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7600523233413696},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7438085675239563},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6933454275131226},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6659600138664246},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5311571359634399},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49821949005126953},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41059935092926025},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2247532606124878}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8859231472015381},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7672461271286011},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7600523233413696},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7438085675239563},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6933454275131226},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6659600138664246},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5311571359634399},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49821949005126953},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41059935092926025},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2247532606124878},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3349567.3351730","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3349567.3351730","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3349567.3351730","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3349567.3351730","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3349567.3351730","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3349567.3351730","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[{"id":"https://openalex.org/G7100125195","display_name":null,"funder_award_id":"CNS-0953447 and CNS-1718033","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2989651171.pdf","grobid_xml":"https://content.openalex.org/works/W2989651171.grobid-xml"},"referenced_works_count":3,"referenced_works":["https://openalex.org/W2128419576","https://openalex.org/W2402144811","https://openalex.org/W2953384591"],"related_works":["https://openalex.org/W1966837078","https://openalex.org/W2167303720","https://openalex.org/W2081416538","https://openalex.org/W2549803267","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W4256652509","https://openalex.org/W2109715593"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"our":[5],"cache":[6,23,32],"configuration":[7,24,33],"prediction":[8],"methodology":[9],"offloaded":[10],"to":[11],"an":[12],"FPGA":[13],"for":[14,34,37],"improved":[15],"performance":[16],"and":[17,40],"hardware":[18],"overhead":[19],"reduction,":[20],"while":[21],"maintaining":[22],"predictions":[25],"within":[26],"5%":[27],"of":[28],"the":[29,38],"optimal":[30],"energy":[31],"application":[35],"phases":[36],"instruction":[39],"data":[41],"caches.":[42]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}