{"id":"https://openalex.org/W2991649285","doi":"https://doi.org/10.1145/3349567.3351726","title":"DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes","display_name":"DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes","publication_year":2019,"publication_date":"2019-10-13","ids":{"openalex":"https://openalex.org/W2991649285","doi":"https://doi.org/10.1145/3349567.3351726","mag":"2991649285"},"language":"en","primary_location":{"id":"doi:10.1145/3349567.3351726","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3349567.3351726","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://dl.acm.org/citation.cfm?id=3349567","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032095821","display_name":"Alessio Burrello","orcid":"https://orcid.org/0000-0002-6215-8220"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Alessio Burrello","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038717922","display_name":"Francesco Conti","orcid":"https://orcid.org/0000-0002-7924-933X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Conti","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052915995","display_name":"Angelo Garofalo","orcid":"https://orcid.org/0000-0002-7495-6895"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Angelo Garofalo","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023905268","display_name":"Davide Rossi","orcid":"https://orcid.org/0000-0002-0651-5393"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Rossi","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5032095821"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":1.4171,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.85799629,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7981674075126648},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6873849630355835},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6440814733505249},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.5637487769126892},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.558826208114624},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.4867241680622101},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.48260343074798584},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4250071048736572},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41686296463012695},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.399186372756958},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3281700015068054},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.160096675157547}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7981674075126648},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6873849630355835},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6440814733505249},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.5637487769126892},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.558826208114624},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.4867241680622101},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.48260343074798584},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4250071048736572},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41686296463012695},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.399186372756958},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3281700015068054},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.160096675157547}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3349567.3351726","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3349567.3351726","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/730310","is_oa":true,"landing_page_url":"http://dl.acm.org/citation.cfm?id=3349567","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:cris.unibo.it:11585/762834","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/762834","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:cris.unibo.it:11585/730310","is_oa":true,"landing_page_url":"http://dl.acm.org/citation.cfm?id=3349567","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2057995607","https://openalex.org/W2117696986","https://openalex.org/W2169500297","https://openalex.org/W2770806677","https://openalex.org/W2889339831","https://openalex.org/W2909953480","https://openalex.org/W3098490553"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2549803267","https://openalex.org/W1976766385","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2125264433","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W4256652509","https://openalex.org/W2109715593"],"abstract_inverted_index":{"IoT":[0],"endnodes":[1],"often":[2],"couple":[3],"a":[4,24,64,118],"small":[5],"and":[6,16,79,98],"fast":[7],"L1":[8],"scratchpad":[9],"memory":[10,39,49,90,136],"with":[11,46,102,108],"higher-capacity":[12],"but":[13,31],"lower":[14],"bandwidth":[15],"speed":[17],"L2":[18,101,135],"background":[19],"memory.":[20],"The":[21],"absence":[22],"of":[23,36,44,87,96],"coherent":[25],"hardware":[26],"cache":[27],"hierarchy":[28],"saves":[29],"energy":[30],"comes":[32],"at":[33],"the":[34,42,85],"cost":[35],"labor-intensive":[37],"explicit":[38],"management,":[40],"complicating":[41],"deployment":[43],"algorithms":[45],"large":[47],"data":[48,77],"footprint,":[50],"such":[51],"as":[52],"Deep":[53],"Neural":[54],"Network":[55],"(DNN)":[56],"inference.":[57],"In":[58],"this":[59],"work,":[60],"we":[61],"present":[62],"DORY,":[63],"lightweight":[65],"software-cache":[66],"dedicated":[67],"to":[68,72,83,110,130],"DNN":[69,121],"Deployment":[70],"Oriented":[71],"memoRY.":[73],"DORY":[74,93],"leverages":[75],"static":[76],"tiling":[78],"DMA-based":[80],"double":[81],"buffering":[82],"hide":[84],"complexity":[86],"manual":[88],"L1-L2":[89],"traffic":[91],"management.":[92],"enables":[94],"storage":[95],"activations":[97],"weights":[99],"in":[100,113],"less":[103,140],"than":[104],"4%":[105],"performance":[106],"overhead":[107],"respect":[109],"direct":[111],"execution":[112,132],"L1.":[114],"We":[115],"show":[116],"that":[117],"142":[119],"kB":[120],"achieving":[122],"79.9%":[123],"on":[124],"CIFAR-10":[125],"runs":[126],"3.2X":[127],"faster":[128],"compared":[129],"its":[131],"directly":[133],"from":[134],"while":[137],"consuming":[138],"1.9X":[139],"energy.":[141]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":10},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2019-12-05T00:00:00"}