{"id":"https://openalex.org/W2961356275","doi":"https://doi.org/10.1145/3337801.3337807","title":"A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation on OpenCL FPGA Platform","display_name":"A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation on OpenCL FPGA Platform","publication_year":2019,"publication_date":"2019-06-06","ids":{"openalex":"https://openalex.org/W2961356275","doi":"https://doi.org/10.1145/3337801.3337807","mag":"2961356275"},"language":"en","primary_location":{"id":"doi:10.1145/3337801.3337807","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3337801.3337807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109330841","display_name":"Changdao Du","orcid":null},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Changdao Du","raw_affiliation_strings":["University of Tsukuba, Tsukuba, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060442383","display_name":"Yoshiki Yamaguchi","orcid":"https://orcid.org/0000-0001-9744-8271"},"institutions":[{"id":"https://openalex.org/I146399215","display_name":"University of Tsukuba","ror":"https://ror.org/02956yf07","country_code":"JP","type":"education","lineage":["https://openalex.org/I146399215"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshiki Yamaguchi","raw_affiliation_strings":["University of Tsukuba, Tsukuba, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tsukuba, Tsukuba, Japan","institution_ids":["https://openalex.org/I146399215"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I146399215"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06054439,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9797000288963318,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11694","display_name":"Fluid Dynamics Simulations and Interactions","score":0.9789999723434448,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8755970001220703},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8215327262878418},{"id":"https://openalex.org/keywords/cellular-automaton","display_name":"Cellular automaton","score":0.6425601840019226},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.61826491355896},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5704790353775024},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.46044787764549255},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43158817291259766},{"id":"https://openalex.org/keywords/vectorization","display_name":"Vectorization (mathematics)","score":0.4176875650882721},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4175604581832886},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37172067165374756},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12915632128715515},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09485727548599243}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8755970001220703},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8215327262878418},{"id":"https://openalex.org/C35527583","wikidata":"https://www.wikidata.org/wiki/Q189156","display_name":"Cellular automaton","level":2,"score":0.6425601840019226},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.61826491355896},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5704790353775024},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.46044787764549255},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43158817291259766},{"id":"https://openalex.org/C41681595","wikidata":"https://www.wikidata.org/wiki/Q7917855","display_name":"Vectorization (mathematics)","level":2,"score":0.4176875650882721},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4175604581832886},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37172067165374756},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12915632128715515},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09485727548599243}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3337801.3337807","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3337801.3337807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W146940060","https://openalex.org/W1496686022","https://openalex.org/W2014786311","https://openalex.org/W2139777359","https://openalex.org/W2497980095","https://openalex.org/W2529513625","https://openalex.org/W2538589664","https://openalex.org/W2785874054","https://openalex.org/W3100822741"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W2126857316","https://openalex.org/W1522032972","https://openalex.org/W2113308450","https://openalex.org/W2139962137","https://openalex.org/W2340647897","https://openalex.org/W3139915793"],"abstract_inverted_index":{"FPGA":[0,18,49],"shows":[1],"its":[2],"potential":[3],"in":[4,9,164],"heterogeneous":[5],"reconfigurable":[6],"computing":[7],"systems":[8],"recent":[10],"years.":[11],"However,":[12],"the":[13,30,46,63,89,99,118],"traditional":[14],"design":[15],"method":[16,84],"of":[17,48,85,91,101,136],"has":[19],"often":[20],"been":[21],"described":[22],"as":[23,54],"Hardware":[24],"Description":[25],"Languages":[26],"(HDL),":[27],"which":[28],"blocked":[29],"way":[31],"that":[32,87],"adopting":[33],"it":[34],"to":[35,44,68,111,141,150],"many":[36],"applications.":[37],"Nevertheless,":[38],"both":[39],"academia":[40],"and":[41,93,108,116,156],"industry":[42],"attempt":[43],"improve":[45],"programmability":[47],"by":[50,97],"using":[51],"high-level":[52],"languages":[53],"a":[55,70,82],"development":[56],"tool.":[57],"In":[58],"this":[59,165],"paper,":[60],"we":[61],"use":[62],"Xilinx":[64,126],"OpenCL":[65],"platform":[66],"SDAccel":[67],"accelerate":[69],"classic":[71],"hydrodynamic":[72],"simulation":[73,113,119,138],"called":[74],"Lattice":[75],"Gas":[76],"Cellular":[77],"Automata":[78],"(LGCA).":[79],"We":[80,121],"introduce":[81],"vectorization":[83],"LGCA":[86,137],"binding":[88],"degree":[90],"execution":[92],"data":[94],"bandwidth":[95],"together":[96],"exploiting":[98],"flexibility":[100],"FPGA.":[102],"This":[103],"work":[104],"also":[105,162],"employs":[106],"spatial":[107],"temporal":[109],"parallelism":[110],"avoid":[112],"size":[114],"restrictions":[115],"increase":[117],"performance.":[120],"evaluate":[122],"our":[123],"technique":[124],"on":[125],"VCU1525":[127],"board":[128],"under":[129],"FHP-III":[130],"collision":[131],"rule":[132],"sets.":[133],"The":[134],"speed":[135],"can":[139],"reach":[140],"maximum":[142],"11073":[143],"million":[144],"hits":[145],"per":[146],"second.":[147],"Comparison":[148],"reports":[149],"an":[151],"Intel":[152],"Core":[153],"i7-6700":[154],"processor":[155],"Nvidia":[157],"Quadro":[158],"P5000":[159],"GPU":[160],"are":[161],"given":[163],"paper.":[166]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
