{"id":"https://openalex.org/W2958388267","doi":"https://doi.org/10.1145/3337801.3337803","title":"An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA","display_name":"An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA","publication_year":2019,"publication_date":"2019-06-06","ids":{"openalex":"https://openalex.org/W2958388267","doi":"https://doi.org/10.1145/3337801.3337803","mag":"2958388267"},"language":"en","primary_location":{"id":"doi:10.1145/3337801.3337803","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3337801.3337803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103940031","display_name":"Hiromu Miyazaki","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Hiromu Miyazaki","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087101846","display_name":"Junya Miura","orcid":null},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Junya Miura","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010523030","display_name":"Kenji Kise","orcid":"https://orcid.org/0000-0002-3003-4872"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenji Kise","raw_affiliation_strings":["School of Computing, Tokyo Institute of Technology, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"School of Computing, Tokyo Institute of Technology, Tokyo, Japan","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103940031"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07526741,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fetch","display_name":"Fetch","score":0.8436452150344849},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7799057960510254},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6775428056716919},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6400913596153259},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6110295653343201},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5649546980857849},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5257357358932495},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.45004189014434814},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44983842968940735},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.41553056240081787},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.38284942507743835},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38093167543411255},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34290409088134766},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.22960230708122253},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.21980881690979004}],"concepts":[{"id":"https://openalex.org/C131918245","wikidata":"https://www.wikidata.org/wiki/Q1409090","display_name":"Fetch","level":2,"score":0.8436452150344849},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7799057960510254},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6775428056716919},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6400913596153259},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6110295653343201},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5649546980857849},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5257357358932495},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.45004189014434814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44983842968940735},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.41553056240081787},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.38284942507743835},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38093167543411255},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34290409088134766},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.22960230708122253},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.21980881690979004},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111368507","wikidata":"https://www.wikidata.org/wiki/Q43518","display_name":"Oceanography","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3337801.3337803","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3337801.3337803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W957890233","https://openalex.org/W2149814460","https://openalex.org/W2186104740","https://openalex.org/W4247271866"],"related_works":["https://openalex.org/W2164026451","https://openalex.org/W2806352516","https://openalex.org/W2148099609","https://openalex.org/W2062172248","https://openalex.org/W2152087194","https://openalex.org/W182515070","https://openalex.org/W4310584696","https://openalex.org/W2538644970","https://openalex.org/W2547383257","https://openalex.org/W4367172762"],"abstract_inverted_index":{"To":[0,52],"reduce":[1],"the":[2,19,23,40,50,54,76,90,95,103,116],"code":[3],"size":[4],"of":[5,42,56],"application":[6],"programs":[7],"for":[8,18],"RISC-V":[9,24],"soft":[10],"processors":[11,47],"on":[12],"an":[13,33],"FPGA,":[14],"it":[15],"is":[16,102],"desirable":[17],"processor":[20],"to":[21],"support":[22,49],"compressed":[25,71,100],"instruction":[26,35,43,57,62],"extension.":[27,51],"In":[28],"this":[29],"paper,":[30],"we":[31,59,92],"implement":[32,75],"efficient":[34],"fetch":[36,63,78,109],"unit.":[37],"We":[38,74],"clarify":[39],"problem":[41,55],"fetching":[44],"in":[45],"pipelining":[46],"that":[48,94],"solve":[53],"fetching,":[58],"propose":[60],"two":[61],"units":[64,79],"using":[65,111],"a":[66,70,99],"decompressed":[67],"cache":[68,101],"and":[69,80,86,105],"cache,":[72],"respectively.":[73],"proposed":[77,96],"evaluate":[81],"their":[82],"performance,":[83],"hardware":[84,113],"resources,":[85],"operating":[87],"frequency.":[88],"Through":[89],"evaluation,":[91],"show":[93],"unit":[97],"with":[98],"best":[104],"achieves":[106],"21.8%":[107],"better":[108],"performance":[110],"reasonable":[112],"resources":[114],"than":[115],"baseline":[117],"architecture.":[118]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}