{"id":"https://openalex.org/W2949537427","doi":"https://doi.org/10.1145/3330345.3330390","title":"Dynamically linked MSHRs for adaptive miss handling in GPUs","display_name":"Dynamically linked MSHRs for adaptive miss handling in GPUs","publication_year":2019,"publication_date":"2019-06-18","ids":{"openalex":"https://openalex.org/W2949537427","doi":"https://doi.org/10.1145/3330345.3330390","mag":"2949537427"},"language":"en","primary_location":{"id":"doi:10.1145/3330345.3330390","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3330345.3330390","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM International Conference on Supercomputing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090471948","display_name":"Yongbin Gu","orcid":"https://orcid.org/0000-0002-5061-0259"},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yongbin Gu","raw_affiliation_strings":["Oregon State University"],"affiliations":[{"raw_affiliation_string":"Oregon State University","institution_ids":["https://openalex.org/I131249849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101894267","display_name":"Lizhong Chen","orcid":"https://orcid.org/0000-0003-0420-0491"},"institutions":[{"id":"https://openalex.org/I131249849","display_name":"Oregon State University","ror":"https://ror.org/00ysfqy60","country_code":"US","type":"education","lineage":["https://openalex.org/I131249849"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lizhong Chen","raw_affiliation_strings":["Oregon State University"],"affiliations":[{"raw_affiliation_string":"Oregon State University","institution_ids":["https://openalex.org/I131249849"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5090471948"],"corresponding_institution_ids":["https://openalex.org/I131249849"],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.4697365,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"510","last_page":"521"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.877881646156311},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7343659400939941},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7056071758270264},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5657237768173218},{"id":"https://openalex.org/keywords/reservation","display_name":"Reservation","score":0.5288242697715759},{"id":"https://openalex.org/keywords/auxiliary-memory","display_name":"Auxiliary memory","score":0.44437968730926514},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42028170824050903},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.41377946734428406},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3041878342628479},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22049206495285034}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.877881646156311},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7343659400939941},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7056071758270264},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5657237768173218},{"id":"https://openalex.org/C2777632111","wikidata":"https://www.wikidata.org/wiki/Q1937518","display_name":"Reservation","level":2,"score":0.5288242697715759},{"id":"https://openalex.org/C82687282","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Auxiliary memory","level":2,"score":0.44437968730926514},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42028170824050903},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.41377946734428406},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3041878342628479},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22049206495285034},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3330345.3330390","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3330345.3330390","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the ACM International Conference on Supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1502175661","https://openalex.org/W1979527452","https://openalex.org/W1982996921","https://openalex.org/W1994999558","https://openalex.org/W2034639175","https://openalex.org/W2047060659","https://openalex.org/W2057352503","https://openalex.org/W2060087084","https://openalex.org/W2065562952","https://openalex.org/W2067441262","https://openalex.org/W2078994750","https://openalex.org/W2080592089","https://openalex.org/W2080756995","https://openalex.org/W2081583983","https://openalex.org/W2084309410","https://openalex.org/W2090584832","https://openalex.org/W2093043622","https://openalex.org/W2100926301","https://openalex.org/W2131413854","https://openalex.org/W2131926352","https://openalex.org/W2132292283","https://openalex.org/W2163820265","https://openalex.org/W2167334577","https://openalex.org/W2169928889","https://openalex.org/W2417236060","https://openalex.org/W2464177207","https://openalex.org/W2511318867","https://openalex.org/W2909808960","https://openalex.org/W3139689176","https://openalex.org/W4233785673","https://openalex.org/W4237024478"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2081416538","https://openalex.org/W2497617944","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W2268996566","https://openalex.org/W4256652509","https://openalex.org/W2140219379"],"abstract_inverted_index":{"Supporting":[0],"a":[1,36,47,95,104,170],"large":[2],"number":[3,38,49,75],"of":[4,39,50,76,106,169,173],"outstanding":[5],"memory":[6,24,77],"requests":[7,78],"in":[8,31,155],"miss":[9],"handling":[10],"architecture":[11],"(MHA)":[12],"is":[13,29,149],"critical":[14],"for":[15],"throughput":[16],"processors":[17],"such":[18],"as":[19,73],"GPUs":[20],"to":[21,42,55,61,70,79,113,125,151],"achieve":[22],"high":[23],"level":[25],"parallelism.":[26],"Conventional":[27],"MHA":[28],"static":[30],"sense":[32],"that":[33,98],"it":[34],"provides":[35],"fixed":[37,48],"MSHR":[40,93,101,160],"entries":[41,102,119,131],"track":[43,56],"primary":[44],"misses,":[45],"and":[46,67,123,164,182,188],"slots":[51,134],"within":[52],"each":[53],"entry":[54,63],"secondary":[57],"misses.":[58],"This":[59,109],"leads":[60],"severe":[62],"or":[64],"slot":[65],"under-utilization":[66],"poor":[68],"match":[69],"practical":[71],"workloads,":[72],"the":[74,143,146,166],"different":[80],"cache":[81],"lines":[82],"can":[83,111],"vary":[84],"significantly.":[85],"In":[86],"this":[87],"paper,":[88],"we":[89],"propose":[90],"Dynamically":[91],"Linked":[92],"(DL-MSHR),":[94],"novel":[96],"approach":[97,110],"dynamically":[99],"forms":[100],"from":[103],"pool":[105],"available":[107],"slots.":[108],"self-adapt":[112,124],"primary-miss-predominant":[114],"applications":[115,127],"by":[116,128,157,162,175],"forming":[117],"more":[118,133],"with":[120,142,179],"fewer":[121,130],"slots,":[122],"secondary-miss-predominant":[126],"having":[129],"but":[132],"per":[135],"entry.":[136],"Evaluation":[137],"results":[138],"show":[139],"that,":[140],"compared":[141],"conventional":[144],"MSHRs,":[145],"proposed":[147],"DL-MSHR":[148],"able":[150],"reduce":[152],"reservation":[153],"fails":[154],"MSHRs":[156],"88.1%,":[158],"improve":[159],"utilization":[161],"53.7%":[163],"increase":[165],"overall":[167],"IPC":[168],"wide":[171],"range":[172],"workloads":[174],"19.2%,":[176],"on":[177,186],"average,":[178],"only":[180],"0.6%":[181],"0.1%":[183],"area":[184],"overhead":[185],"L1D":[187],"L2":[189],"cache,":[190],"respectively.":[191]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
