{"id":"https://openalex.org/W2945120490","doi":"https://doi.org/10.1145/3316781.3322467","title":"An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis","display_name":"An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis","publication_year":2019,"publication_date":"2019-05-23","ids":{"openalex":"https://openalex.org/W2945120490","doi":"https://doi.org/10.1145/3316781.3322467","mag":"2945120490"},"language":"en","primary_location":{"id":"doi:10.1145/3316781.3322467","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3322467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 56th Annual Design Automation Conference 2019","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062117190","display_name":"Po-Cheng Pan","orcid":"https://orcid.org/0000-0002-8626-1249"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Cheng Pan","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067537031","display_name":"Chien-Chia Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Chia Huang","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu City, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7392542362213135},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.7295050621032715},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.599850058555603},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5297620892524719},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4808695912361145},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.46052485704421997},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4104440212249756},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36647504568099976},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.36434391140937805},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.32955944538116455},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25423622131347656},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15108391642570496},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1261119544506073},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11377763748168945}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7392542362213135},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.7295050621032715},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.599850058555603},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5297620892524719},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4808695912361145},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.46052485704421997},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4104440212249756},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36647504568099976},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.36434391140937805},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.32955944538116455},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25423622131347656},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15108391642570496},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1261119544506073},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11377763748168945},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3316781.3322467","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3322467","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 56th Annual Design Automation Conference 2019","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1593974800","https://openalex.org/W1999063830","https://openalex.org/W2166106792","https://openalex.org/W4231987538"],"related_works":["https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2007222089","https://openalex.org/W2394022884","https://openalex.org/W2185815555","https://openalex.org/W2071235072","https://openalex.org/W1924227955","https://openalex.org/W4242038055","https://openalex.org/W1493881961","https://openalex.org/W2375192119"],"abstract_inverted_index":{"An":[0],"efficient":[1],"synthesis":[2],"technique":[3],"for":[4,38],"modern":[5],"analog":[6,22,43,86],"circuits":[7,87],"is":[8,30],"important":[9],"yet":[10],"challenging":[11],"due":[12],"to":[13,66,91],"the":[14,21,27,40,48,69],"repeatedly":[15],"re-synthesis":[16],"process.":[17],"To":[18],"precisely":[19],"explore":[20],"circuit":[23],"performance":[24,73,97],"limitation":[25,41],"on":[26,84],"required":[28],"technology":[29],"time-consuming.":[31],"This":[32],"work":[33],"presents":[34],"a":[35],"learning-based":[36],"framework":[37],"searching":[39],"of":[42,50],"circuits.":[44],"With":[45],"hierarchical":[46],"architecture,":[47],"dimension":[49],"solution":[51],"space":[52],"can":[53,75,88],"be":[54,76],"reduced.":[55],"Bayesian":[56],"linear":[57],"regression":[58],"and":[59,71],"support":[60],"vector":[61],"machine":[62],"model":[63],"are":[64],"selected":[65],"speed":[67],"up":[68,90],"algorithm":[70],"better":[72],"quality":[74],"retrieved.":[77],"Experimental":[78],"results":[79],"show":[80],"that":[81],"our":[82],"approach":[83],"two":[85],"achieve":[89],"9x":[92],"runtime":[93],"speed-up":[94],"without":[95],"surrendering":[96],"qualities.":[98]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}