{"id":"https://openalex.org/W2944848421","doi":"https://doi.org/10.1145/3316781.3317860","title":"MARCH","display_name":"MARCH","publication_year":2019,"publication_date":"2019-05-23","ids":{"openalex":"https://openalex.org/W2944848421","doi":"https://doi.org/10.1145/3316781.3317860","mag":"2944848421"},"language":"en","primary_location":{"id":"doi:10.1145/3316781.3317860","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3317860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 56th Annual Design Automation Conference 2019","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101951915","display_name":"Jingsong Chen","orcid":"https://orcid.org/0000-0001-9867-9805"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":true,"raw_author_name":"Jingsong Chen","raw_affiliation_strings":["CSE Department, CUHK"],"affiliations":[{"raw_affiliation_string":"CSE Department, CUHK","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091445235","display_name":"Jinwei Liu","orcid":"https://orcid.org/0000-0001-8161-5004"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Jinwei Liu","raw_affiliation_strings":["CSE Department, CUHK"],"affiliations":[{"raw_affiliation_string":"CSE Department, CUHK","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052177721","display_name":"Gengjie Chen","orcid":"https://orcid.org/0000-0001-6016-4742"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Gengjie Chen","raw_affiliation_strings":["CSE Department, CUHK"],"affiliations":[{"raw_affiliation_string":"CSE Department, CUHK","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049129612","display_name":"Daniel Zheng","orcid":"https://orcid.org/0009-0006-4523-6262"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Dan Zheng","raw_affiliation_strings":["CSE Department, CUHK"],"affiliations":[{"raw_affiliation_string":"CSE Department, CUHK","institution_ids":["https://openalex.org/I889458895"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I889458895","display_name":"University of Hong Kong","ror":"https://ror.org/02zhqgq86","country_code":"HK","type":"education","lineage":["https://openalex.org/I889458895"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["CSE Department, CUHK"],"affiliations":[{"raw_affiliation_string":"CSE Department, CUHK","institution_ids":["https://openalex.org/I889458895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101951915"],"corresponding_institution_ids":["https://openalex.org/I889458895"],"apc_list":null,"apc_paid":null,"fwci":0.9538,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.75645239,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7759382724761963},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7529805898666382},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6960521936416626},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5978555083274841},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5924215912818909},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5378903746604919},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5232231020927429},{"id":"https://openalex.org/keywords/hierarchical-routing","display_name":"Hierarchical routing","score":0.46599259972572327},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.4420831799507141},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.38933950662612915},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38733816146850586},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33160191774368286},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3287108242511749},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.2844694256782532},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.26736968755722046},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1408231258392334},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12043678760528564}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7759382724761963},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7529805898666382},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6960521936416626},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5978555083274841},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5924215912818909},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5378903746604919},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5232231020927429},{"id":"https://openalex.org/C177818476","wikidata":"https://www.wikidata.org/wiki/Q12878103","display_name":"Hierarchical routing","level":5,"score":0.46599259972572327},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.4420831799507141},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.38933950662612915},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38733816146850586},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33160191774368286},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3287108242511749},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.2844694256782532},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.26736968755722046},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1408231258392334},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12043678760528564},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3316781.3317860","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3316781.3317860","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 56th Annual Design Automation Conference 2019","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2052259763","https://openalex.org/W2053902150","https://openalex.org/W2058646559","https://openalex.org/W2122851474","https://openalex.org/W2143764757","https://openalex.org/W2151278468","https://openalex.org/W2801260432","https://openalex.org/W2900068574","https://openalex.org/W2908860223"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W61292821","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W4205718258","https://openalex.org/W1989674257","https://openalex.org/W2152063629","https://openalex.org/W4231567751","https://openalex.org/W4237042129"],"abstract_inverted_index":{"The":[0],"continuous":[1],"development":[2],"of":[3,95],"modern":[4],"VLSI":[5],"technology":[6],"has":[7],"brought":[8],"new":[9],"challenges":[10],"for":[11,65,106],"on-chip":[12],"interconnections.":[13],"Different":[14],"from":[15],"classic":[16],"net-by-net":[17],"routing,":[18],"bus":[19,29,79],"routing":[20,57],"requires":[21],"all":[22,74],"the":[23,27,35,71,75,120,129],"nets":[24],"(bits)":[25],"in":[26,77,85,136],"same":[28,36,72],"to":[30,69,117],"share":[31],"similar":[32],"or":[33],"even":[34],"topology,":[37,73],"besides":[38],"considering":[39],"wire":[40],"length,":[41],"via":[42],"count,":[43],"and":[44,62,101,112,139],"other":[45],"design":[46],"rules.":[47],"In":[48,67,123],"this":[49],"paper,":[50],"we":[51],"present":[52],"MARCH,":[53,68],"an":[54,109],"efficient":[55],"maze":[56],"method":[58,91],"under":[59],"a":[60,78,86,96,102],"concurrent":[61],"hierarchical":[63],"scheme":[64,114],"buses.":[66],"achieve":[70],"bits":[76],"are":[80],"routed":[81],"concurrently":[82],"like":[83],"marching":[84],"path.":[87],"For":[88],"efficiency,":[89],"our":[90],"is":[92,115],"hierarchical,":[93],"consisting":[94],"coarse-grained":[97],"topology-aware":[98],"path":[99],"planning":[100],"fine-grained":[103],"track":[104],"assignment":[105],"bits.":[107],"Additionally,":[108],"effective":[110],"rip-up":[111],"reroute":[113],"applied":[116],"further":[118],"improve":[119],"solution":[121],"quality.":[122],"experimental":[124],"results,":[125],"MARCH":[126],"significantly":[127],"outperforms":[128],"first":[130],"place":[131],"at":[132],"2018":[133],"IC/CAD":[134],"Contest":[135],"both":[137],"quality":[138],"runtime.":[140]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2019-05-29T00:00:00"}