{"id":"https://openalex.org/W2935994026","doi":"https://doi.org/10.1145/3299902.3311064","title":"Advances in Adaptable Computing","display_name":"Advances in Adaptable Computing","publication_year":2019,"publication_date":"2019-04-04","ids":{"openalex":"https://openalex.org/W2935994026","doi":"https://doi.org/10.1145/3299902.3311064","mag":"2935994026"},"language":"en","primary_location":{"id":"doi:10.1145/3299902.3311064","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299902.3311064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101523397","display_name":"Amit Kumar Gupta","orcid":"https://orcid.org/0000-0002-2875-5216"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Amit Gupta","raw_affiliation_strings":["Xilinx Inc, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5101523397"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":0.9631,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72084529,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"37","last_page":"38"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7733150124549866},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6077566146850586},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5471644401550293},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5323793292045593},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.450457364320755},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.44505369663238525},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4444849491119385},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4312010109424591},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.4244329631328583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41468656063079834},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36915117502212524},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.2731250822544098},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2597394287586212}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7733150124549866},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6077566146850586},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5471644401550293},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5323793292045593},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.450457364320755},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.44505369663238525},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4444849491119385},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4312010109424591},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.4244329631328583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41468656063079834},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36915117502212524},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.2731250822544098},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2597394287586212},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3299902.3311064","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299902.3311064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2036895660","https://openalex.org/W2606722458"],"related_works":["https://openalex.org/W2384867379","https://openalex.org/W4400094300","https://openalex.org/W2329539859","https://openalex.org/W2227905990","https://openalex.org/W2765823764","https://openalex.org/W3214280620","https://openalex.org/W3191490922","https://openalex.org/W2794038527","https://openalex.org/W2327638088","https://openalex.org/W2151092287"],"abstract_inverted_index":{"Recent":[0,73],"technical":[1,74],"challenges":[2,36,75],"have":[3,105,250],"forced":[4,106],"the":[5,11,52,69,77,83,100,107,120],"industry":[6,122],"to":[7,38,61,111,132,223,254],"explore":[8],"options":[9],"beyond":[10],"conventional":[12],"\"one":[13,85],"size":[14,86],"fits":[15,87],"all\"":[16,88],"CPU":[17,89],"scalar":[18,90],"processing":[19,24,140,160,187],"solution.":[20],"Very":[21],"large":[22],"vector":[23],"(DSP,":[25],"GPU)":[26],"solves":[27],"some":[28],"problems,":[29],"but":[30,51,180,203,247],"it":[31],"runs":[32],"into":[33],"traditional":[34,53,84],"scaling":[35,81,98,104],"due":[37],"inflexible,":[39],"inefficient":[40],"memory":[41,49,213],"bandwidth":[42],"usage.":[43],"Traditional":[44],"FPGA":[45],"solutions":[46],"provide":[47],"programmable":[48,146],"hierarchy,":[50],"hardware":[54,147],"development":[55],"flow":[56],"has":[57],"been":[58],"a":[59,118,175,196,224],"barrier":[60],"broad,":[62],"high-volume":[63],"adoption":[64],"in":[65,76,94,183],"application":[66],"spaces":[67],"like":[68],"Data":[70],"Center":[71],"market.":[72],"semiconductor":[78,95,121],"process":[79,96],"prevent":[80],"of":[82,102,178,199,211],"compute":[91,201,226],"engine.":[92],"Changes":[93],"frequency":[97],"with":[99,170],"end":[101],"Dennard":[103],"standard":[108],"computing":[109],"elements":[110,161,188],"become":[112],"increasingly":[113],"multicore":[114],"[Ref":[115],"1].":[116],"As":[117],"result,":[119],"is":[123,154],"exploring":[124],"alternate":[125],"domain-specific":[126],"architectures,":[127],"including":[128],"ones":[129],"previously":[130],"relegated":[131],"specific":[133],"extreme":[134],"performance":[135,184],"segments":[136],"such":[137],"as":[138],"vector-based":[139],"(DSPs,":[141],"GPUs)":[142,191],"and":[143,174,207,240],"fully":[144],"parallel":[145],"(FPGAs).":[148],"The":[149],"question":[150],"becomes:":[151],"Which":[152],"architecture":[153],"best":[155,231],"for":[156],"which":[157,228],"task?":[158],"Scalar":[159],"(e.g.,":[162,189,217,236,244],"CPUs)":[163],"are":[164,181,192],"very":[165],"efficient":[166,194],"at":[167,195,232],"complex":[168],"algorithms":[169],"diverse":[171],"decision":[172],"trees":[173],"broad":[176],"set":[177,198],"libraries":[179],"limited":[182],"scaling.":[185],"Vector":[186],"DSPs,":[190],"more":[193],"narrower":[197],"parallelizable":[200],"functions,":[202],"they":[204],"experience":[205],"latency":[206],"efficiency":[208],"penalties":[209],"because":[210],"inflexible":[212],"hierarchy.":[214],"Programmable":[215],"logic":[216],"FPGAs)":[218],"can":[219],"be":[220],"precisely":[221],"customized":[222],"particular":[225],"function,":[227],"makes":[229],"them":[230],"latency-critical":[233],"real-time":[234],"applications":[235],"automotive":[237],"driver-assist,":[238],"ADAS)":[239],"irregular":[241],"data":[242],"structures":[243],"genomic":[245],"sequencing),":[246],"algorithmic":[248],"changes":[249],"traditionally":[251],"taken":[252],"hours":[253],"compile":[255],"versus":[256],"minutes.":[257]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}