{"id":"https://openalex.org/W2937099099","doi":"https://doi.org/10.1145/3299902.3309755","title":"Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement","display_name":"Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement","publication_year":2019,"publication_date":"2019-04-04","ids":{"openalex":"https://openalex.org/W2937099099","doi":"https://doi.org/10.1145/3299902.3309755","mag":"2937099099"},"language":"en","primary_location":{"id":"doi:10.1145/3299902.3309755","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299902.3309755","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074859640","display_name":"Hua-Yu Chang","orcid":"https://orcid.org/0000-0001-8324-0592"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Hua-Yu Chang","raw_affiliation_strings":["Synopsys, Inc., Taipei, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Taipei, Taiwan Roc","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031004106","display_name":"Iris Hui-Ru Jiang","orcid":"https://orcid.org/0000-0002-4554-3442"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Iris Hui-Ru Jiang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan Roc"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan Roc","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074859640"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1192,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.43585281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"93","last_page":"100"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11245","display_name":"Advanced Numerical Analysis Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2206","display_name":"Computational Mechanics"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10996","display_name":"Computational Geometry and Mesh Generation","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1704","display_name":"Computer Graphics and Computer-Aided Design"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/polygon","display_name":"Polygon (computer graphics)","score":0.664999783039093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6052409410476685},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5860097408294678},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5528820157051086},{"id":"https://openalex.org/keywords/topology-optimization","display_name":"Topology optimization","score":0.5500900745391846},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5467856526374817},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.49514856934547424},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.4894184172153473},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.47970813512802124},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4206925630569458},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.418666273355484},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2834411859512329},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18387383222579956},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15033504366874695},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1297665238380432},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09848597645759583}],"concepts":[{"id":"https://openalex.org/C190694206","wikidata":"https://www.wikidata.org/wiki/Q3276654","display_name":"Polygon (computer graphics)","level":3,"score":0.664999783039093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6052409410476685},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5860097408294678},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5528820157051086},{"id":"https://openalex.org/C189216461","wikidata":"https://www.wikidata.org/wiki/Q2443456","display_name":"Topology optimization","level":3,"score":0.5500900745391846},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5467856526374817},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.49514856934547424},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.4894184172153473},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.47970813512802124},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4206925630569458},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.418666273355484},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2834411859512329},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18387383222579956},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15033504366874695},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1297665238380432},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09848597645759583},{"id":"https://openalex.org/C135628077","wikidata":"https://www.wikidata.org/wiki/Q220184","display_name":"Finite element method","level":2,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3299902.3309755","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299902.3309755","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320309545","display_name":"Synopsys","ror":"https://ror.org/013by2m91"},{"id":"https://openalex.org/F4320322589","display_name":"Taiwan Semiconductor Manufacturing Company","ror":"https://ror.org/02wx79d08"},{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1971739315","https://openalex.org/W1983920947","https://openalex.org/W1996288366","https://openalex.org/W1999678814","https://openalex.org/W2083274833","https://openalex.org/W2093576521","https://openalex.org/W2116621052","https://openalex.org/W2143286762","https://openalex.org/W2213088056","https://openalex.org/W2342679249","https://openalex.org/W2594817995"],"related_works":["https://openalex.org/W2124495928","https://openalex.org/W2096129555","https://openalex.org/W2097517502","https://openalex.org/W2129355781","https://openalex.org/W4363620137","https://openalex.org/W2161137937","https://openalex.org/W4233404530","https://openalex.org/W2052733504","https://openalex.org/W2152479836","https://openalex.org/W2134016418"],"abstract_inverted_index":{"Multiple":[0],"patterning":[1,157],"lithography":[2,35],"(MPL)":[3],"divides":[4],"a":[5,14,38,70,120,176],"layout":[6,39,44,47,63,71,82,123,158,173,206],"into":[7],"several":[8],"masks":[9,99],"and":[10,18,33,46,57,94,101,136,141,170,186,200],"manufactures":[11],"them":[12],"by":[13,40,79],"series":[15],"of":[16,29,97,168,188],"exposure":[17],"etching":[19],"steps.":[20],"As":[21,67],"technology":[22,107],"advances,":[23],"MPL":[24,41],"is":[25,84,113,125,198],"still":[26],"indispensable":[27],"because":[28,96],"its":[30],"cost":[31],"effectiveness":[32,187],"hybrid":[34],"capability.":[36],"Producing":[37],"relies":[42],"on":[43],"decomposition":[45],"compliance.":[48,159],"The":[49],"former":[50],"reports":[51],"conflicts":[52],"(i.e.,":[53],"identifies":[54],"undecomposable":[55],"polygons),":[56],"the":[58,62,150,172,183],"latter":[59],"further":[60],"modifies":[61],"to":[64,127,132,137,204],"clean":[65],"conflicts.":[66],"long":[68],"as":[69,175],"has":[72],"unresolved":[73],"conflicts,":[74,135],"it":[75],"cannot":[76],"be":[77,202],"manufactured":[78],"MPL.":[80,87],"Hence,":[81],"compliance":[83],"crucial":[85],"for":[86,155],"This":[88],"task,":[89],"however,":[90],"becomes":[91],"more":[92,98],"complicated":[93],"challenging":[95],"used":[100],"design":[102],"rule":[103],"explosion":[104],"at":[105],"advanced":[106],"nodes.":[108],"Semi-automation":[109],"or":[110],"manual":[111],"fixing":[112,207],"thus":[114],"no":[115],"longer":[116],"applicable.":[117],"Moreover,":[118],"from":[119],"designer's":[121],"perspective,":[122],"modification":[124],"desired":[126],"preserve":[128],"interconnect":[129],"correctness,":[130],"not":[131],"create":[133],"new":[134],"minimize":[138],"topology":[139,166,192],"disturbance":[140],"polygon":[142,177],"displacement.":[143],"Therefore,":[144],"in":[145],"this":[146,162],"paper,":[147],"we":[148,164],"propose":[149],"first":[151],"fully":[152],"automatic":[153],"approach":[154],"multiple":[156],"For":[160],"achieving":[161],"goal,":[163],"extract":[165],"relations":[167],"polygons":[169],"model":[171],"correction":[174],"legalization":[178],"problem.":[179],"Experimental":[180],"results":[181],"demonstrate":[182],"superior":[184],"efficiency":[185],"our":[189,194],"approach.":[190],"With":[191],"awareness,":[193],"spacing":[195],"constraint":[196],"handling":[197],"general":[199],"can":[201],"applied":[203],"other":[205],"problems.":[208]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}