{"id":"https://openalex.org/W2937184059","doi":"https://doi.org/10.1145/3299902.3309749","title":"Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing","display_name":"Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing","publication_year":2019,"publication_date":"2019-04-04","ids":{"openalex":"https://openalex.org/W2937184059","doi":"https://doi.org/10.1145/3299902.3309749","mag":"2937184059"},"language":"en","primary_location":{"id":"doi:10.1145/3299902.3309749","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3299902.3309749","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3299902.3309749","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3299902.3309749","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016037177","display_name":"Sheng-En David Lin","orcid":"https://orcid.org/0009-0000-2235-5695"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheng-En David Lin","raw_affiliation_strings":["Washington State University, Pullman, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington State University, Pullman, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100374561","display_name":"Dae Hyun Kim","orcid":"https://orcid.org/0000-0001-8275-5949"},"institutions":[{"id":"https://openalex.org/I72951846","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17","country_code":"US","type":"education","lineage":["https://openalex.org/I72951846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dae Hyun Kim","raw_affiliation_strings":["Washington State University, Washington State University, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington State University, Washington State University, WA, USA","institution_ids":["https://openalex.org/I72951846"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I72951846"],"apc_list":null,"apc_paid":null,"fwci":0.1211,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.44416662,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"57","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6702224016189575},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.6000432372093201},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5996341705322266},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5970798134803772},{"id":"https://openalex.org/keywords/steiner-tree-problem","display_name":"Steiner tree problem","score":0.5459309220314026},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.5049417614936829},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.4675793945789337},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.43539413809776306},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3671001195907593},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3616819977760315},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.347930371761322},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25505706667900085},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.20870211720466614},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20749765634536743},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13917240500450134},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.13747170567512512},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09460064768791199}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6702224016189575},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.6000432372093201},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5996341705322266},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5970798134803772},{"id":"https://openalex.org/C76220878","wikidata":"https://www.wikidata.org/wiki/Q1764144","display_name":"Steiner tree problem","level":2,"score":0.5459309220314026},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.5049417614936829},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.4675793945789337},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.43539413809776306},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3671001195907593},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3616819977760315},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.347930371761322},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25505706667900085},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.20870211720466614},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20749765634536743},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13917240500450134},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.13747170567512512},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09460064768791199},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3299902.3309749","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3299902.3309749","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3299902.3309749","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3299902.3309749","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3299902.3309749","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3299902.3309749","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 International Symposium on Physical Design","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[{"id":"https://openalex.org/G6916104274","display_name":null,"funder_award_id":"D16AP00119","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"},{"id":"https://openalex.org/G73391826","display_name":null,"funder_award_id":"125679-002","funder_id":"https://openalex.org/F4320309913","funder_display_name":"Washington State University"}],"funders":[{"id":"https://openalex.org/F4320309913","display_name":"Washington State University","ror":"https://ror.org/05dk0ce17"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2937184059.pdf","grobid_xml":"https://content.openalex.org/works/W2937184059.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W2002806561","https://openalex.org/W2037342223","https://openalex.org/W2048927144","https://openalex.org/W2125831674","https://openalex.org/W2130923737","https://openalex.org/W2142927985","https://openalex.org/W2163262984","https://openalex.org/W2569250791","https://openalex.org/W2611777290","https://openalex.org/W2790641181","https://openalex.org/W2791191785"],"related_works":["https://openalex.org/W2016970881","https://openalex.org/W2333804548","https://openalex.org/W1990828594","https://openalex.org/W2945692190","https://openalex.org/W3093450488","https://openalex.org/W2027159884","https://openalex.org/W2016589506","https://openalex.org/W3047088815","https://openalex.org/W3015807029","https://openalex.org/W4389383710"],"abstract_inverted_index":{"Monolithic":[0],"three-dimensional~(3D)":[1],"integration":[2],"enables":[3],"stacking":[4],"multiple":[5],"ultra-thin":[6],"silicon":[7],"tiers":[8],"in":[9,73],"a":[10,92],"single":[11],"package,":[12],"thereby":[13],"providing":[14],"smaller":[15],"footprint":[16],"area,":[17],"shorter":[18],"wirelength,":[19],"higher":[20],"performance,":[21],"and":[22,51,80,128],"lower":[23],"power":[24],"consumption":[25],"than":[26],"conventional":[27],"planar":[28],"fabrication":[29],"technologies.":[30],"Physical":[31],"design":[32,40],"of":[33,123,132],"monolithic":[34,76,104],"3D":[35,44,46,49,52,57,68,111,118,134],"integrated":[36],"circuits~(ICs)":[37],"requires":[38],"several":[39],"steps":[41],"such":[42],"as":[43],"placement,":[45],"clock-tree":[47],"synthesis,":[48],"routing,":[50],"optimization.":[53],"Among":[54],"the":[55,110,121,124,130,133],"steps,":[56],"routing":[58,65,69,93],"is":[59,70],"very":[60],"time-consuming":[61],"due":[62],"to":[63,90,100],"numerous":[64],"blockages.":[66],"Thus,":[67],"typically":[71],"performed":[72],"two":[74],"sub-steps,":[75],"inter-layer":[77],"via~(MIV)":[78],"insertion":[79,126],"tier-by-tier":[81],"routing.":[82,135],"In":[83],"this":[84],"paper,":[85],"we":[86],"propose":[87],"an":[88],"algorithm":[89],"build":[91],"topology":[94],"database":[95,115],"that":[96],"can":[97],"be":[98],"used":[99],"construct":[101],"all":[102],"multilayer":[103],"rectilinear":[105],"Steiner":[106],"minimum":[107],"trees":[108],"on":[109],"Hanan":[112],"grid.":[113],"The":[114],"will":[116],"help":[117],"routers":[119],"reduce":[120],"runtime":[122],"MIV":[125],"step":[127],"improve":[129],"quality":[131]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}