{"id":"https://openalex.org/W2945087116","doi":"https://doi.org/10.1145/3299874.3318035","title":"An Analytical-based Hybrid Algorithm for FPGA Placement","display_name":"An Analytical-based Hybrid Algorithm for FPGA Placement","publication_year":2019,"publication_date":"2019-05-13","ids":{"openalex":"https://openalex.org/W2945087116","doi":"https://doi.org/10.1145/3299874.3318035","mag":"2945087116"},"language":"en","primary_location":{"id":"doi:10.1145/3299874.3318035","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299874.3318035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014548453","display_name":"Chengyu Hu","orcid":"https://orcid.org/0000-0001-8226-5747"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chengyu Hu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000918972","display_name":"Qinghua Duan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qinghua Duan","raw_affiliation_strings":["Chengdu Sino Microelectronic Technology Co., Ltd, Chengdu, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chengdu Sino Microelectronic Technology Co., Ltd, Chengdu, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022087642","display_name":"Li-Ran Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liran Hu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025981776","display_name":"Peng Lu","orcid":"https://orcid.org/0000-0003-0743-1068"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Lu","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101963402","display_name":"Zhengjie Li","orcid":"https://orcid.org/0000-0002-2918-2800"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhengjie Li","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005595160","display_name":"Meng Yang","orcid":"https://orcid.org/0000-0003-2862-2015"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Meng Yang","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017286601","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-0229-4199"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1211,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.44832874,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"351","last_page":"354"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8537002801895142},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.8161261677742004},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7740612626075745},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.751015305519104},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6118814945220947},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5799431800842285},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.5279910564422607},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5087409615516663},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.42245227098464966},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4166105091571808},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4133869707584381},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17344525456428528},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.13577750325202942},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.10524362325668335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07220375537872314}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8537002801895142},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.8161261677742004},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7740612626075745},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.751015305519104},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6118814945220947},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5799431800842285},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.5279910564422607},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5087409615516663},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.42245227098464966},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4166105091571808},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4133869707584381},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17344525456428528},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.13577750325202942},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.10524362325668335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07220375537872314},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3299874.3318035","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299874.3318035","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1986026297","https://openalex.org/W2005602803","https://openalex.org/W2020549672","https://openalex.org/W2063510738","https://openalex.org/W2075137913","https://openalex.org/W2114820519","https://openalex.org/W2138206217","https://openalex.org/W2142613770","https://openalex.org/W2154302973","https://openalex.org/W2164340799","https://openalex.org/W2526849555","https://openalex.org/W6669537989"],"related_works":["https://openalex.org/W1875577501","https://openalex.org/W1968931833","https://openalex.org/W4245174233","https://openalex.org/W2122425352","https://openalex.org/W108855261","https://openalex.org/W2098132017","https://openalex.org/W4244167835","https://openalex.org/W2031837447","https://openalex.org/W2101527510","https://openalex.org/W2105236412"],"abstract_inverted_index":{"As":[0],"the":[1,94],"capacity":[2],"of":[3,69,74,105,129],"FPGA":[4,6],"increases,":[5],"placers":[7],"that":[8],"adopt":[9],"Simulated":[10],"Annealing":[11],"(SA)":[12],"algorithm":[13,29,88],"take":[14],"more":[15,17],"and":[16,33,46,65,76,83,111,127],"runtime.":[18],"To":[19],"solve":[20],"this":[21,23],"problem,":[22],"paper":[24],"presents":[25],"HCAS,":[26],"a":[27,103],"Hybrid":[28],"Combining":[30],"Analytical":[31],"method":[32],"SA.":[34,70],"There":[35],"are":[36],"three":[37],"modifications":[38],"in":[39,93],"HCAS:":[40],"(1)":[41],"In":[42,56],"global":[43,82],"placement,":[44,58],"faster":[45],"better":[47],"result":[48],"is":[49,61,78,91,132],"realized":[50],"by":[51],"modified":[52],"analytical":[53],"algorithm.":[54],"(2)":[55],"detailed":[57,84],"proper":[59],"tradeoff":[60],"made":[62],"between":[63,81],"quality":[64,131],"runtime":[66],"through":[67],"improvement":[68],"(3)":[71],"Optimization":[72],"workload":[73],"timing":[75],"wirelength":[77,110],"reasonably":[79],"assigned":[80],"placement":[85,130],"according":[86],"to":[87,98,118],"features.":[89],"HCAS":[90,123],"implemented":[92],"newest":[95],"VPR.":[96],"Compared":[97,117],"VPR":[99],"placer,":[100],"it":[101],"obtains":[102],"speedup":[104,126],"11.1x,":[106],"with":[107],"3%":[108],"shorter":[109],"5%":[112],"smaller":[113],"critical":[114],"path":[115],"delay.":[116],"other":[119],"analytical-based":[120],"hybrid":[121],"placers,":[122],"achieves":[124],"greater":[125],"enhancement":[128],"similar":[133],"or":[134],"better.":[135]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}