{"id":"https://openalex.org/W2946743980","doi":"https://doi.org/10.1145/3299874.3317976","title":"Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis","display_name":"Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis","publication_year":2019,"publication_date":"2019-05-13","ids":{"openalex":"https://openalex.org/W2946743980","doi":"https://doi.org/10.1145/3299874.3317976","mag":"2946743980"},"language":"en","primary_location":{"id":"doi:10.1145/3299874.3317976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299874.3317976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080012092","display_name":"S. Sanyal","orcid":"https://orcid.org/0000-0002-6652-9113"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sayandeep Sanyal","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022978241","display_name":"Shan Pavan Pani Krishna Garapati","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shan Pavan Pani Krishna Garapati","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102706209","display_name":"Amit Patra","orcid":"https://orcid.org/0000-0002-3996-5761"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Patra","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103922058","display_name":"Mayukh Bhattacharya","orcid":"https://orcid.org/0009-0002-4111-4648"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mayukh Bhattacharya","raw_affiliation_strings":["Synopsys Inc., San Francisco, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys Inc., San Francisco, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9872,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73373006,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"123","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6217759847640991},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6024547219276428},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5890024900436401},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.5872254967689514},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5618454813957214},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.5464020371437073},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5116660594940186},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48977160453796387},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4783436954021454},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.44471877813339233},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3453202247619629},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3080154061317444},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28714999556541443},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16199463605880737},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08815795183181763}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6217759847640991},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6024547219276428},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5890024900436401},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.5872254967689514},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5618454813957214},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.5464020371437073},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5116660594940186},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48977160453796387},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4783436954021454},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.44471877813339233},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3453202247619629},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3080154061317444},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28714999556541443},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16199463605880737},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08815795183181763},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3299874.3317976","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3299874.3317976","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320309545","display_name":"Synopsys","ror":"https://ror.org/013by2m91"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1966190965","https://openalex.org/W1978212282","https://openalex.org/W1980913384","https://openalex.org/W1994721348","https://openalex.org/W2042256779","https://openalex.org/W2044500680","https://openalex.org/W2088797164","https://openalex.org/W2119157332","https://openalex.org/W2131374318","https://openalex.org/W2134344610","https://openalex.org/W2137111266","https://openalex.org/W2144061903","https://openalex.org/W2147819306","https://openalex.org/W2245005569","https://openalex.org/W2496582029","https://openalex.org/W2782226720"],"related_works":["https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2007222089","https://openalex.org/W2031235560","https://openalex.org/W3147038789","https://openalex.org/W2171636001","https://openalex.org/W4234197374","https://openalex.org/W4318953393","https://openalex.org/W1985049148","https://openalex.org/W1578030032"],"abstract_inverted_index":{"Detection":[0],"of":[1,52,90,111,119,135,154,174,193],"faults":[2,33,125,145,160,196],"in":[3,34,61,81,126,157],"a":[4,12,38,42,109,133,187],"mixed-signal":[5,65],"SOC":[6],"at":[7],"the":[8,22,53,62,120,144,152,194],"pre-silicon":[9],"stage":[10],"is":[11,36],"challenge,":[13],"especially":[14],"when":[15],"it":[16],"has":[17,58],"substantial":[18],"analog":[19,27,63,82,127],"components.":[20],"Given":[21],"time":[23],"taken":[24],"for":[25,72],"simulating":[26],"circuits,":[28,83],"designing":[29],"tests":[30],"to":[31,98,107,122,142,185],"detect":[32,143],"them":[35],"not":[37,86],"straightforward":[39],"task.":[40],"Achieving":[41],"high":[43,163,188],"fault":[44,96,164,175,189],"coverage":[45,165,190],"without":[46],"doing":[47],"extensive":[48],"time-consuming":[49],"transient":[50],"simulation":[51],"circuit":[54],"under":[55],"test":[56,69],"(CUT)":[57],"remained":[59],"elusive":[60],"and":[64,93,116,161,177],"(AMS)":[66],"domain.":[67],"Unlike":[68],"generation":[70],"approach":[71,156],"digital":[73],"designs":[74],"which":[75,138],"leverage":[76],"logical":[77,91],"equivalence":[78],"between":[79],"faults,":[80],"there":[84],"does":[85],"exist":[87],"any":[88],"notion":[89],"equivalence,":[92],"therefore":[94],"each":[95],"needs":[97],"be":[99,140],"treated":[100],"independently.":[101],"In":[102],"this":[103,155],"paper,":[104],"we":[105,181],"propose":[106],"use":[108],"combination":[110],"DC":[112],"operating":[113],"point":[114],"analysis":[115,118],"AC":[117],"CUT":[121],"identify":[123],"equivalent":[124,159],"circuits.":[128],"We":[129],"also":[130],"put":[131],"forward":[132],"methodology":[134,173],"synthesizing":[136],"inputs":[137],"will":[139],"able":[141,184],"during":[146],"post-silicon":[147],"testing.":[148],"Our":[149],"studies":[150],"reveal":[151],"effectiveness":[153],"identifying":[158],"achieving":[162],"with":[166],"considerably":[167],"reduced":[168],"computations.":[169],"By":[170],"using":[171],"proposed":[172],"classification":[176],"input":[178],"signal":[179],"synthesis,":[180],"have":[182],"been":[183],"achieve":[186],"where":[191],"most":[192],"detectable":[195],"are":[197],"successfully":[198],"covered.":[199]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
