{"id":"https://openalex.org/W2917169168","doi":"https://doi.org/10.1145/3289602.3294000","title":"HOTMeTaL","display_name":"HOTMeTaL","publication_year":2019,"publication_date":"2019-02-20","ids":{"openalex":"https://openalex.org/W2917169168","doi":"https://doi.org/10.1145/3289602.3294000","mag":"2917169168"},"language":"en","primary_location":{"id":"doi:10.1145/3289602.3294000","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3294000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086530026","display_name":"Michael Kapralos","orcid":"https://orcid.org/0000-0002-8820-9858"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Kapralos","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082629462","display_name":"John A. Chandy","orcid":"https://orcid.org/0000-0003-3449-3205"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Chandy","raw_affiliation_strings":["University of Connecticut, storrs, CT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Connecticut, storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01214431,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"307","last_page":"308"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7509603500366211},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6139126420021057},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5942649841308594},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5801989436149597},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5682188272476196},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5232537984848022},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5215266346931458},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5207133889198303},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5069180130958557},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4910154342651367},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4744252562522888},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4552350342273712},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4456169605255127},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4417078197002411},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.43124568462371826},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41414687037467957},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4074819087982178},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3863392174243927},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2529330849647522},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13812878727912903}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7509603500366211},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6139126420021057},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5942649841308594},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5801989436149597},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5682188272476196},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5232537984848022},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5215266346931458},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5207133889198303},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5069180130958557},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4910154342651367},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4744252562522888},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4552350342273712},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4456169605255127},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4417078197002411},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.43124568462371826},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41414687037467957},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4074819087982178},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3863392174243927},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2529330849647522},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13812878727912903},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3289602.3294000","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3294000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W115147118","https://openalex.org/W1583974916","https://openalex.org/W1941428497","https://openalex.org/W1993937043","https://openalex.org/W1995215165","https://openalex.org/W2018094844","https://openalex.org/W2032195315","https://openalex.org/W2117215427","https://openalex.org/W2128953988","https://openalex.org/W2145897936","https://openalex.org/W2162250345","https://openalex.org/W2171549192","https://openalex.org/W2242458479","https://openalex.org/W2335478831","https://openalex.org/W2482880624","https://openalex.org/W2583971000","https://openalex.org/W2588538322","https://openalex.org/W2768047339","https://openalex.org/W2786101043","https://openalex.org/W4232747210"],"related_works":["https://openalex.org/W2994343469","https://openalex.org/W2102777336","https://openalex.org/W3105918491","https://openalex.org/W1905312773","https://openalex.org/W2490069675","https://openalex.org/W2197466303","https://openalex.org/W2139569078","https://openalex.org/W2359075490","https://openalex.org/W2128907153","https://openalex.org/W4206484832"],"abstract_inverted_index":{"FPGA":[0,59],"designs":[1],"are":[2],"typically":[3],"optimized":[4],"for":[5,38,98],"speed":[6],"and":[7,22,41],"accuracy,":[8,21],"with":[9,47,153],"the":[10,17,34,54,74,86,90,106,121,133,141,144,148,172,180],"amount":[11,173],"of":[12,56,76,89,108,123,143,150,174],"available":[13],"hardware":[14,23],"considered":[15],"after":[16],"fact.":[18],"Balancing":[19],"speed,":[20],"utilization":[24],"is":[25,68,80,162],"a":[26,70,137],"difficult":[27],"proposition.":[28],"In":[29],"this":[30,48,151],"paper,":[31],"we":[32,103,146],"demonstrate":[33,147],"Hardware":[35],"Optimization":[36],"Tool":[37],"Memory":[39],"Table":[40],"Logic":[42],"Conversion":[43],"(HOTMeTaL)":[44],"which":[45,118],"helps":[46],"tradeoff":[49],"by":[50],"modifying":[51],"part":[52],"or":[53,72,110],"majority":[55],"an":[57],"existing":[58],"design":[60],"to":[61,156],"use":[62,75],"additional":[63],"logic":[64,79,100,116,175],"resources":[65,134],"when":[66,78],"memory":[67,77],"at":[69],"premium,":[71],"force":[73],"highly":[81],"utilized;":[82],"without":[83],"significantly":[84],"changing":[85],"overall":[87],"functionality":[88],"design.":[91,138],"Using":[92],"established":[93],"minimization":[94],"methods,":[95],"traditionally":[96],"used":[97,135],"programmable":[99],"devices":[101],"(PLDs),":[102],"also":[104],"allow":[105],"conversion":[107],"groups":[109],"individual":[111],"output":[112],"bits":[113],"into":[114],"minimal":[115],"circuits,":[117],"then":[119],"allows":[120],"creation":[122],"several":[124],"functionally":[125],"identical":[126],"designs,":[127],"but":[128],"allowing":[129],"more":[130],"control":[131],"over":[132],"in":[136,165],"After":[139],"introducing":[140],"basics":[142],"algorithm,":[145],"utility":[149],"process":[152],"direct":[154],"comparisons":[155],"examples":[157],"from":[158],"previous":[159],"works.":[160],"It":[161],"demonstrated":[163],"that":[164],"some":[166],"cases,":[167],"our":[168],"system":[169],"will":[170],"reduce":[171],"(slices)":[176],"while":[177],"simultaneously":[178],"removing":[179]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2019-03-02T00:00:00"}