{"id":"https://openalex.org/W2915780780","doi":"https://doi.org/10.1145/3289602.3293900","title":"Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching","display_name":"Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching","publication_year":2019,"publication_date":"2019-02-20","ids":{"openalex":"https://openalex.org/W2915780780","doi":"https://doi.org/10.1145/3289602.3293900","mag":"2915780780"},"language":"en","primary_location":{"id":"doi:10.1145/3289602.3293900","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3293900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066761150","display_name":"Zhiyuan Shao","orcid":"https://orcid.org/0000-0003-2139-6465"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyuan Shao","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101621723","display_name":"Ruoshi Li","orcid":"https://orcid.org/0009-0002-8027-4695"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruoshi Li","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102158554","display_name":"Diqing Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Diqing Hu","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022398389","display_name":"Xiaofei Liao","orcid":"https://orcid.org/0000-0001-6302-813X"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaofei Liao","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022262922","display_name":"Hai Jin","orcid":"https://orcid.org/0000-0002-3934-7605"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hai Jin","raw_affiliation_strings":["Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I47720641"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"320","last_page":"329"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11273","display_name":"Advanced Graph Neural Networks","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8091943264007568},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5388983488082886},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5163951516151428},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49013933539390564},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.48767173290252686},{"id":"https://openalex.org/keywords/pagerank","display_name":"PageRank","score":0.42198628187179565},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4173317849636078},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37878286838531494},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27147176861763},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.15392720699310303}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8091943264007568},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5388983488082886},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5163951516151428},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49013933539390564},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.48767173290252686},{"id":"https://openalex.org/C2779172887","wikidata":"https://www.wikidata.org/wiki/Q184316","display_name":"PageRank","level":2,"score":0.42198628187179565},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4173317849636078},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37878286838531494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27147176861763},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.15392720699310303}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3289602.3293900","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3293900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1832683484","https://openalex.org/W1955594754","https://openalex.org/W1976969221","https://openalex.org/W2053076698","https://openalex.org/W2072605585","https://openalex.org/W2085426754","https://openalex.org/W2111823238","https://openalex.org/W2113513143","https://openalex.org/W2152872804","https://openalex.org/W2157534438","https://openalex.org/W2162639668","https://openalex.org/W2170616854","https://openalex.org/W2282294254","https://openalex.org/W2284169075","https://openalex.org/W2324639061","https://openalex.org/W2508029414","https://openalex.org/W2583135230","https://openalex.org/W2584785188","https://openalex.org/W2606413522","https://openalex.org/W2788601541","https://openalex.org/W2789007918","https://openalex.org/W2950542868","https://openalex.org/W2997134027"],"related_works":["https://openalex.org/W2154222238","https://openalex.org/W2106626222","https://openalex.org/W3120961607","https://openalex.org/W2980866815","https://openalex.org/W4401568740","https://openalex.org/W3148568549","https://openalex.org/W1562405179","https://openalex.org/W2125493559","https://openalex.org/W1544909909","https://openalex.org/W2098207691"],"abstract_inverted_index":{"In":[0,95],"recent":[1],"years,":[2],"graph":[3,31,43,110,130,226],"processing":[4,29,44,90,111,227],"attracts":[5],"lots":[6],"of":[7,28,42,73,92,109,119,129,225],"attention":[8],"due":[9],"to":[10,54,105,139,163,185],"its":[11],"broad":[12],"applicability":[13],"in":[14,70,209,221],"solving":[15],"real-world":[16],"problems.":[17],"With":[18],"the":[19,26,30,39,56,79,89,93,107,117,127,176,198,214,223],"flexibility":[20],"and":[21,58,83,123,154,165,172,183,187,194],"programmability,":[22],"FPGA":[23,177,199],"platforms":[24,114],"provide":[25],"opportunity":[27],"data":[32,75,121],"with":[33,50,179,201],"high":[34],"efficiency.":[35],"On":[36],"FPGA-DRAM":[37,113,229],"platforms,":[38],"state-of-art":[40],"solution":[41],"(i.e.,":[45],"ForeGraph)":[46],"attaches":[47],"each":[48],"pipeline":[49,85,124],"local":[51],"vertex":[52,65,74,102,120,143,216],"buffers":[53],"cache":[55],"source":[57],"destination":[59],"vertices":[60],"during":[61,126],"processing.":[62],"Such":[63],"one-level":[64],"caching":[66,103,144,217],"mechanism,":[67],"however,":[68],"results":[69,157],"excessive":[71],"amounts":[72,118],"transmissions":[76,122],"that":[77,87,213],"consume":[78],"precious":[80],"DRAM":[81],"bandwidth,":[82],"frequent":[84],"stalls":[86,125],"waste":[88],"power":[91],"FPGA.":[94],"this":[96,210],"paper,":[97],"we":[98],"propose":[99],"a":[100,134],"two-level":[101,142,215],"mechanism":[104,145],"improve":[106],"performance":[108,224],"on":[112,175,197,228],"by":[115,146],"reducing":[116],"execution":[128],"algorithms.":[131],"We":[132],"build":[133],"system,":[135],"named":[136],"as":[137],"FabGraph,":[138],"implement":[140],"such":[141],"using":[147],"available":[148],"on-chip":[149],"storage":[150],"resources,":[151],"including":[152],"BRAM":[153,203],"UltraRAM.":[155,206],"Experimental":[156],"show":[158],"that:":[159],"FabGraph":[160],"achieves":[161],"up":[162,184],"3.1x":[164,186],"2.5x":[166],"speedups":[167,189],"over":[168,190],"ForeGraph":[169,191],"for":[170,192],"BFS":[171,193],"PageRank":[173,195],"respectively,":[174,196],"board":[178,200],"relatively":[180],"large":[181,205],"BRAM;":[182],"3.0x":[188],"small":[202],"but":[204],"Our":[207],"experience":[208],"paper":[211],"suggests":[212],"design":[218],"is":[219],"effective":[220],"improving":[222],"platforms.":[230]},"counts_by_year":[{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}