{"id":"https://openalex.org/W2915733502","doi":"https://doi.org/10.1145/3289602.3293897","title":"Simultaneous Placement and Clock Tree Construction for Modern FPGAs","display_name":"Simultaneous Placement and Clock Tree Construction for Modern FPGAs","publication_year":2019,"publication_date":"2019-02-20","ids":{"openalex":"https://openalex.org/W2915733502","doi":"https://doi.org/10.1145/3289602.3293897","mag":"2915733502"},"language":"en","primary_location":{"id":"doi:10.1145/3289602.3293897","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3293897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034982668","display_name":"Wuxi Li","orcid":"https://orcid.org/0000-0002-9887-5109"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wuxi Li","raw_affiliation_strings":["University of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069832936","display_name":"Mehrdad Eslami Dehkordi","orcid":"https://orcid.org/0000-0001-7663-4059"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mehrdad E. Dehkordi","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066133332","display_name":"Stephen Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Yang","raw_affiliation_strings":["Xilinx Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Xilinx Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5034982668"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.7262,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.70939104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"132","last_page":"141"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7342678308486938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7174909710884094},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6088502407073975},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5893685817718506},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5868724584579468},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5800254344940186},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5176544785499573},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5060593485832214},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.49014052748680115},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.48120859265327454},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4644505977630615},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43001246452331543},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32471662759780884},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2947689890861511},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.17149287462234497}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7342678308486938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7174909710884094},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6088502407073975},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5893685817718506},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5868724584579468},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5800254344940186},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5176544785499573},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5060593485832214},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.49014052748680115},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.48120859265327454},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4644505977630615},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43001246452331543},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32471662759780884},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2947689890861511},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17149287462234497},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3289602.3293897","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3289602.3293897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1965195759","https://openalex.org/W1969483458","https://openalex.org/W1977545325","https://openalex.org/W1986026297","https://openalex.org/W2020549672","https://openalex.org/W2055251702","https://openalex.org/W2057469119","https://openalex.org/W2111756578","https://openalex.org/W2137454730","https://openalex.org/W2139637699","https://openalex.org/W2144931885","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2328615082","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2595334824","https://openalex.org/W2626482350","https://openalex.org/W2738078952","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2886092906","https://openalex.org/W2886700560","https://openalex.org/W2897282114","https://openalex.org/W4236384091","https://openalex.org/W4249211602"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2144282137","https://openalex.org/W3006003651","https://openalex.org/W2127892766"],"abstract_inverted_index":{"Modern":[0],"field-programmable":[1],"gate":[2],"array":[3],"(FPGA)":[4],"devices":[5],"often":[6,73],"contain":[7],"complex":[8],"clocking":[9],"architectures":[10],"to":[11,47,64],"achieve":[12,144],"high-performance":[13],"and":[14,29,44,78,105,118],"flexible":[15],"clock":[16,23,42,48,56,66,75,107,111,137],"networks.":[17],"The":[18],"physical":[19],"structure":[20],"of":[21,120],"these":[22,87],"networks,":[24],"however,":[25,71],"are":[26],"pre-manufactured,":[27],"unadjustable,":[28],"with":[30,134,149],"only":[31],"limited":[32],"routing":[33,49,57,76],"resources.":[34],"Most":[35],"conventional":[36],"FPGA":[37,96],"placement":[38,82,97,103],"algorithms":[39],"rarely":[40],"consider":[41],"feasibility,":[43],"therefore":[45],"lead":[46],"failures.":[50],"Some":[51],"recent":[52],"works":[53],"adopt":[54],"simplified":[55],"models":[58],"(e.g.,":[59],"the":[60,116,121,125,140,145],"bounding":[61],"box":[62],"model)":[63],"force":[65],"legality":[67],"during":[68],"placement,":[69],"which,":[70],"can":[72,100,143],"overestimate":[74],"demands":[77],"results":[79],"in":[80,89],"unnecessary":[81],"quality":[83,104],"degradation.":[84],"To":[85],"address":[86],"limitations,":[88],"this":[90],"paper,":[91],"we":[92],"propose":[93],"a":[94],"generic":[95],"framework":[98],"that":[99],"simultaneously":[101],"optimize":[102],"ensure":[106],"feasibility":[108],"by":[109],"explicit":[110],"tree":[112],"construction.":[113],"We":[114],"demonstrate":[115],"effectiveness":[117],"efficiency":[119],"proposed":[122,141],"approach":[123,142],"using":[124],"ISPD":[126],"2017":[127],"Clock-Aware":[128],"Placement":[129],"Contest":[130],"benchmark":[131],"suite.":[132],"Compared":[133],"other":[135],"state-of-the-art":[136],"legalization":[138],"algorithms,":[139],"best":[146],"routed":[147],"wirelength":[148],"competitive":[150],"runtime.":[151]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-04-07T06:01:17.266235","created_date":"2025-10-10T00:00:00"}