{"id":"https://openalex.org/W2910269697","doi":"https://doi.org/10.1145/3287624.3287756","title":"Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS","display_name":"Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS","publication_year":2019,"publication_date":"2019-01-18","ids":{"openalex":"https://openalex.org/W2910269697","doi":"https://doi.org/10.1145/3287624.3287756","mag":"2910269697"},"language":"en","primary_location":{"id":"doi:10.1145/3287624.3287756","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3287624.3287756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044148031","display_name":"Atsuki Kobayashi","orcid":"https://orcid.org/0000-0002-3279-4007"},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Atsuki Kobayashi","raw_affiliation_strings":["Nagoya University, Nagoya, Japan"],"affiliations":[{"raw_affiliation_string":"Nagoya University, Nagoya, Japan","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080365891","display_name":"Yuya Nishio","orcid":"https://orcid.org/0000-0002-0028-5507"},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuya Nishio","raw_affiliation_strings":["Nagoya University, Nagoya, Japan"],"affiliations":[{"raw_affiliation_string":"Nagoya University, Nagoya, Japan","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056883187","display_name":"Kenya Hayashi","orcid":"https://orcid.org/0000-0001-8421-7458"},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenya Hayashi","raw_affiliation_strings":["Nagoya University, Nagoya, Japan"],"affiliations":[{"raw_affiliation_string":"Nagoya University, Nagoya, Japan","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077948074","display_name":"Shigeki Arata","orcid":"https://orcid.org/0000-0001-9332-1820"},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shigeki Arata","raw_affiliation_strings":["Nagoya University, Nagoya, Japan"],"affiliations":[{"raw_affiliation_string":"Nagoya University, Nagoya, Japan","institution_ids":["https://openalex.org/I60134161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056677721","display_name":"Kiichi Niitsu","orcid":"https://orcid.org/0000-0002-3813-3955"},"institutions":[{"id":"https://openalex.org/I60134161","display_name":"Nagoya University","ror":"https://ror.org/04chrp450","country_code":"JP","type":"education","lineage":["https://openalex.org/I60134161"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kiichi Niitsu","raw_affiliation_strings":["Nagoya University, Nagoya, Japan and JST/PRESTO, Saitama, Japan"],"affiliations":[{"raw_affiliation_string":"Nagoya University, Nagoya, Japan and JST/PRESTO, Saitama, Japan","institution_ids":["https://openalex.org/I60134161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5044148031"],"corresponding_institution_ids":["https://openalex.org/I60134161"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00430634,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"9","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timer","display_name":"Timer","score":0.6801307201385498},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6579930782318115},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6566126346588135},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.561151385307312},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5282779335975647},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.527518093585968},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5272083878517151},{"id":"https://openalex.org/keywords/replica","display_name":"Replica","score":0.5204394459724426},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4969828426837921},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.4701433479785919},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42319706082344055},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.42030075192451477},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30971306562423706}],"concepts":[{"id":"https://openalex.org/C2776633867","wikidata":"https://www.wikidata.org/wiki/Q186612","display_name":"Timer","level":3,"score":0.6801307201385498},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6579930782318115},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6566126346588135},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.561151385307312},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5282779335975647},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.527518093585968},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5272083878517151},{"id":"https://openalex.org/C2775937380","wikidata":"https://www.wikidata.org/wiki/Q1232589","display_name":"Replica","level":2,"score":0.5204394459724426},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4969828426837921},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.4701433479785919},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42319706082344055},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.42030075192451477},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30971306562423706},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3287624.3287756","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3287624.3287756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th Asia and South Pacific Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7799999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1973359205"],"related_works":["https://openalex.org/W3013979739","https://openalex.org/W2360439717","https://openalex.org/W2655578171","https://openalex.org/W2577913821","https://openalex.org/W2460131733","https://openalex.org/W2388292776","https://openalex.org/W2953070151","https://openalex.org/W4296976839","https://openalex.org/W2372946558","https://openalex.org/W2765214557"],"abstract_inverted_index":{"A":[0],"design":[1],"of":[2,63,70],"gate-leakage-based":[3],"timer":[4],"using":[5],"an":[6,59],"amplifier-less":[7],"replica-bias":[8],"switching":[9],"technique":[10],"that":[11,27],"can":[12],"realize":[13],"stable":[14,22],"and":[15,41],"low-voltage":[16],"operation":[17],"is":[18,44],"presented.":[19],"To":[20],"generate":[21],"oscillation":[23],"frequency,":[24],"the":[25,29],"topology":[26],"discharges":[28],"pre-charged":[30],"capacitor":[31,37],"via":[32],"a":[33,67,74],"gate":[34],"leaking":[35],"MOS":[36],"with":[38],"low-leakage":[39],"switch":[40],"logic":[42],"circuits":[43],"employed.":[45],"The":[46],"test":[47],"chip":[48],"fabricated":[49],"in":[50,73],"55-nm":[51],"deeply":[52],"depleted":[53],"channel":[54],"(DDC)":[55],"CMOS":[56],"technology":[57],"achieves":[58],"Allan":[60],"deviation":[61],"floor":[62],"200":[64],"ppm":[65],"at":[66],"supply":[68],"voltage":[69],"350":[71],"mV":[72],"0.0022":[75],"mm2":[76],"area.":[77]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
