{"id":"https://openalex.org/W2900091459","doi":"https://doi.org/10.1145/3274281","title":"Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis","display_name":"Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis","publication_year":2018,"publication_date":"2018-09-30","ids":{"openalex":"https://openalex.org/W2900091459","doi":"https://doi.org/10.1145/3274281","mag":"2900091459"},"language":"en","primary_location":{"id":"doi:10.1145/3274281","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3274281","pdf_url":null,"source":{"id":"https://openalex.org/S136160450","display_name":"ACM Transactions on Embedded Computing Systems","issn_l":"1539-9087","issn":["1539-9087","1558-3465"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Embedded Computing Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069864154","display_name":"Mohamed Hassan","orcid":"https://orcid.org/0000-0001-5926-5861"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Mohamed Hassan","raw_affiliation_strings":["University of Waterloo, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073862711","display_name":"Anirudh Mohan Kaushik","orcid":"https://orcid.org/0000-0002-8347-0109"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Anirudh M. Kaushik","raw_affiliation_strings":["University of Waterloo, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074065388","display_name":"Hiren Patel","orcid":"https://orcid.org/0000-0003-2750-4471"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Hiren Patel","raw_affiliation_strings":["University of Waterloo, ON, Canada"],"affiliations":[{"raw_affiliation_string":"University of Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5069864154"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.14446346,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"17","issue":"5","first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9097591638565063},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7636474370956421},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7475273609161377},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6624276041984558},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.646163284778595},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5679267644882202},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5651466250419617},{"id":"https://openalex.org/keywords/reverse-engineering","display_name":"Reverse engineering","score":0.5479129552841187},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3572278320789337},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34622132778167725},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33386942744255066},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23670640587806702}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9097591638565063},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7636474370956421},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7475273609161377},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6624276041984558},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.646163284778595},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5679267644882202},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5651466250419617},{"id":"https://openalex.org/C207850805","wikidata":"https://www.wikidata.org/wiki/Q269608","display_name":"Reverse engineering","level":2,"score":0.5479129552841187},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3572278320789337},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34622132778167725},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33386942744255066},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23670640587806702},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3274281","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3274281","pdf_url":null,"source":{"id":"https://openalex.org/S136160450","display_name":"ACM Transactions on Embedded Computing Systems","issn_l":"1539-9087","issn":["1539-9087","1558-3465"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Embedded Computing Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1496414880","https://openalex.org/W1504046403","https://openalex.org/W1515422725","https://openalex.org/W1543670042","https://openalex.org/W1606804836","https://openalex.org/W1793246495","https://openalex.org/W1959279725","https://openalex.org/W1981191435","https://openalex.org/W1981588964","https://openalex.org/W1991739900","https://openalex.org/W2015827499","https://openalex.org/W2017239768","https://openalex.org/W2034861439","https://openalex.org/W2050143636","https://openalex.org/W2092160538","https://openalex.org/W2102800454","https://openalex.org/W2110195531","https://openalex.org/W2114052814","https://openalex.org/W2116826559","https://openalex.org/W2118296780","https://openalex.org/W2128544270","https://openalex.org/W2148543770","https://openalex.org/W2157116240","https://openalex.org/W2162639668","https://openalex.org/W2165683591","https://openalex.org/W2165697076","https://openalex.org/W2167233984","https://openalex.org/W2184585965","https://openalex.org/W2239632431","https://openalex.org/W2346166411","https://openalex.org/W2612242064","https://openalex.org/W2616807090","https://openalex.org/W2619943509","https://openalex.org/W2786904362","https://openalex.org/W2897114489","https://openalex.org/W2964118667","https://openalex.org/W3083310154","https://openalex.org/W4229487452"],"related_works":["https://openalex.org/W1976244802","https://openalex.org/W4293430534","https://openalex.org/W2335743642","https://openalex.org/W4297812927","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W2154976966","https://openalex.org/W2542815272","https://openalex.org/W3140615508","https://openalex.org/W2029945810"],"abstract_inverted_index":{"We":[0,45,63],"explore":[1],"techniques":[2],"to":[3,22,53,59,82],"reverse-engineer":[4],"DRAM":[5],"embedded":[6,32],"memory":[7],"controllers":[8],"(MCs),":[9],"including":[10],"page":[11],"policies,":[12,87],"address":[13],"mapping,":[14],"and":[15,34,42,56,93],"command":[16],"arbitration.":[17],"There":[18],"are":[19],"several":[20],"benefits":[21],"knowing":[23],"this":[24],"information:":[25],"They":[26],"allow":[27],"tightening":[28],"worst-case":[29],"bounds":[30],"of":[31,67,86],"systems":[33],"platform-aware":[35],"optimizations":[36],"at":[37],"the":[38,65,68,73,77],"operating":[39],"system,":[40],"source-code,":[41],"compiler":[43],"levels.":[44],"develop":[46],"a":[47,84,90],"latency-based":[48],"analysis,":[49],"which":[50],"we":[51,88],"use":[52,89],"devise":[54],"algorithms":[55],"C":[57],"programs":[58],"extract":[60],"MC":[61,74],"properties.":[62],"show":[64],"effectiveness":[66],"proposed":[69],"approach":[70],"by":[71],"reverse-engineering":[72],"details":[75],"in":[76],"XUPV5-LX110T":[78],"Xilinx":[79],"platform.":[80],"Furthermore,":[81],"cover":[83],"breadth":[85],"simulation":[91],"framework":[92],"document":[94],"our":[95],"findings.":[96]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
