{"id":"https://openalex.org/W2903140524","doi":"https://doi.org/10.1145/3273957","title":"A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation","display_name":"A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation","publication_year":2018,"publication_date":"2018-10-31","ids":{"openalex":"https://openalex.org/W2903140524","doi":"https://doi.org/10.1145/3273957","mag":"2903140524"},"language":"en","primary_location":{"id":"doi:10.1145/3273957","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3273957","pdf_url":null,"source":{"id":"https://openalex.org/S96198239","display_name":"ACM Journal on Emerging Technologies in Computing Systems","issn_l":"1550-4832","issn":["1550-4832","1550-4840"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Journal on Emerging Technologies in Computing Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000245553","display_name":"Zhongyang Liu","orcid":"https://orcid.org/0000-0002-3371-2392"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhongyang Liu","raw_affiliation_strings":["Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068988480","display_name":"Shaoheng Luo","orcid":null},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaoheng Luo","raw_affiliation_strings":["Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071529609","display_name":"Xiaowei Xu","orcid":"https://orcid.org/0000-0002-1046-6379"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaowei Xu","raw_affiliation_strings":["University of Notre Dame, IN, USA"],"raw_orcid":"https://orcid.org/0000-0002-1046-6379","affiliations":[{"raw_affiliation_string":"University of Notre Dame, IN, USA","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000141831","display_name":"Yiyu Shi","orcid":"https://orcid.org/0000-0002-6788-9823"},"institutions":[{"id":"https://openalex.org/I107639228","display_name":"University of Notre Dame","ror":"https://ror.org/00mkhxb43","country_code":"US","type":"education","lineage":["https://openalex.org/I107639228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiyu Shi","raw_affiliation_strings":["University of Notre Dame, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Notre Dame, IN, USA","institution_ids":["https://openalex.org/I107639228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054211420","display_name":"Cheng Zhuo","orcid":"https://orcid.org/0000-0002-2610-7522"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cheng Zhuo","raw_affiliation_strings":["Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5000245553"],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":1.9633,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.8736285,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"14","issue":"4","first_page":"1","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8202956318855286},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7734231948852539},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7445780038833618},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7329468131065369},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5491745471954346},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.49710729718208313},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.48728954792022705},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4695739448070526},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.45608043670654297},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45107996463775635},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.42606598138809204},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3793925642967224},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3309081494808197},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.2817966938018799},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23579353094100952},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11489254236221313}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8202956318855286},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7734231948852539},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7445780038833618},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7329468131065369},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5491745471954346},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.49710729718208313},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.48728954792022705},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4695739448070526},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.45608043670654297},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45107996463775635},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.42606598138809204},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3793925642967224},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3309081494808197},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.2817966938018799},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23579353094100952},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11489254236221313},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3273957","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3273957","pdf_url":null,"source":{"id":"https://openalex.org/S96198239","display_name":"ACM Journal on Emerging Technologies in Computing Systems","issn_l":"1550-4832","issn":["1550-4832","1550-4840"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Journal on Emerging Technologies in Computing Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W41027960","https://openalex.org/W177004468","https://openalex.org/W1893455912","https://openalex.org/W1995473414","https://openalex.org/W1998865404","https://openalex.org/W2001297728","https://openalex.org/W2017410652","https://openalex.org/W2028195847","https://openalex.org/W2030814277","https://openalex.org/W2035009069","https://openalex.org/W2050127689","https://openalex.org/W2056515096","https://openalex.org/W2063572467","https://openalex.org/W2072497408","https://openalex.org/W2085677136","https://openalex.org/W2093462371","https://openalex.org/W2094756095","https://openalex.org/W2100309045","https://openalex.org/W2117148079","https://openalex.org/W2130097981","https://openalex.org/W2130478168","https://openalex.org/W2133589264","https://openalex.org/W2185878459","https://openalex.org/W2292208776","https://openalex.org/W2306317764","https://openalex.org/W2315049132","https://openalex.org/W2527193322","https://openalex.org/W2528596247","https://openalex.org/W2546366412","https://openalex.org/W2799462322","https://openalex.org/W2800130919","https://openalex.org/W3140285855","https://openalex.org/W3146026292","https://openalex.org/W3161797085"],"related_works":["https://openalex.org/W1500978221","https://openalex.org/W2115380918","https://openalex.org/W4282568311","https://openalex.org/W3133116121","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W4285346947","https://openalex.org/W4288420200","https://openalex.org/W3145095675","https://openalex.org/W3205973659"],"abstract_inverted_index":{"Cellular":[0],"Neural":[1],"Network":[2],"(CeNN)":[3],"is":[4,111],"considered":[5],"as":[6],"a":[7,97],"powerful":[8],"paradigm":[9],"for":[10,100],"embedded":[11],"devices.":[12],"Its":[13],"analog":[14],"and":[15,30,37,44,60,67,89,119,126,146],"mix-signal":[16],"hardware":[17],"implementations":[18,49,73,103,154],"are":[19,74],"proved":[20],"to":[21,24,63,78,148],"be":[22],"applicable":[23],"high-speed":[25],"image":[26],"processing,":[27],"video":[28],"analysis,":[29],"medical":[31],"signal":[32],"processing":[33],"with":[34,86,113,121,134,152,155],"its":[35,64],"efficiency":[36],"popularity":[38],"limited":[39],"by":[40],"smaller":[41],"implementation":[42],"size":[43],"lower":[45],"precision.":[46],"Recently,":[47],"digital":[48],"of":[50,83,144],"CeNNs":[51],"on":[52,104,123],"FPGA":[53,84],"have":[54],"attracted":[55],"researchers":[56],"from":[57],"both":[58],"academia":[59],"industry":[61],"due":[62],"high":[65],"flexibility":[66],"short":[68],"time-to-market.":[69],"However,":[70],"most":[71],"existing":[72,153],"not":[75],"well":[76],"optimized":[77],"fully":[79],"utilize":[80],"the":[81,108],"advantages":[82],"platform":[85],"unnecessary":[87],"design":[88],"computational":[90,124],"redundancy":[91,125],"that":[92,133],"prevents":[93],"speedup.":[94],"We":[95],"propose":[96],"multi-level-optimization":[98],"framework":[99,110,138],"energy-efficient":[101],"CeNN":[102],"FPGAs.":[105],"In":[106],"particular,":[107],"optimization":[109],"featured":[112],"three":[114],"level":[115],"optimizations:":[116],"system-,":[117],"module-,":[118],"design-space-level,":[120],"focus":[122],"attainable":[127],"performance,":[128],"respectively.":[129],"Experimental":[130],"results":[131],"show":[132],"various":[135],"configurations":[136],"our":[137],"can":[139],"achieve":[140],"an":[141],"energy-efficiency":[142],"improvement":[143],"3.54\u00d7":[145],"up":[147],"3.88\u00d7":[149],"speedup":[150],"compared":[151],"similar":[156],"accuracy.":[157]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
