{"id":"https://openalex.org/W2899799513","doi":"https://doi.org/10.1145/3240765.3240847","title":"Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems","display_name":"Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems","publication_year":2018,"publication_date":"2018-11-05","ids":{"openalex":"https://openalex.org/W2899799513","doi":"https://doi.org/10.1145/3240765.3240847","mag":"2899799513"},"language":"en","primary_location":{"id":"doi:10.1145/3240765.3240847","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240765.3240847","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035783996","display_name":"Shih-Chun Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Shih-Chun Chen","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 106, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 106, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111538908","display_name":"Richard Sun","orcid":"https://orcid.org/0009-0003-3924-2154"},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Richard Sun","raw_affiliation_strings":["Synopsys Inc","Synopsys Inc., Mountain View, CA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc","institution_ids":["https://openalex.org/I1335490905"]},{"raw_affiliation_string":"Synopsys Inc., Mountain View, CA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 106, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 106, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5035783996"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":1.8246,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.86396431,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7550009489059448},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7502678632736206},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6412268877029419},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6343119740486145},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5603797435760498},{"id":"https://openalex.org/keywords/time-division-multiplexing","display_name":"Time-division multiplexing","score":0.5168817043304443},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.46276727318763733},{"id":"https://openalex.org/keywords/division","display_name":"Division (mathematics)","score":0.4478677809238434},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4422883093357086},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.42958173155784607},{"id":"https://openalex.org/keywords/time-complexity","display_name":"Time complexity","score":0.4129989743232727},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3705868124961853},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35706448554992676},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3269050717353821},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.293961763381958},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.19072139263153076},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14836150407791138},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09097269177436829},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.08063986897468567}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7550009489059448},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7502678632736206},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6412268877029419},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6343119740486145},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5603797435760498},{"id":"https://openalex.org/C50661577","wikidata":"https://www.wikidata.org/wiki/Q901831","display_name":"Time-division multiplexing","level":3,"score":0.5168817043304443},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.46276727318763733},{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.4478677809238434},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4422883093357086},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.42958173155784607},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.4129989743232727},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3705868124961853},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35706448554992676},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3269050717353821},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.293961763381958},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.19072139263153076},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14836150407791138},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09097269177436829},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.08063986897468567},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3240765.3240847","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240765.3240847","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1992578807","https://openalex.org/W2023428606","https://openalex.org/W2050456603","https://openalex.org/W2063893206","https://openalex.org/W2078174680","https://openalex.org/W2095117703","https://openalex.org/W2109220922","https://openalex.org/W2148658001","https://openalex.org/W2336648157","https://openalex.org/W2789489838","https://openalex.org/W2793619867"],"related_works":["https://openalex.org/W1987487129","https://openalex.org/W4380987687","https://openalex.org/W2164654367","https://openalex.org/W1968897524","https://openalex.org/W2169510384","https://openalex.org/W1962246972","https://openalex.org/W2086835975","https://openalex.org/W1483430493","https://openalex.org/W2032253216","https://openalex.org/W2121263056"],"abstract_inverted_index":{"The":[0],"2.5D":[1,25],"FPGA":[2,14,26],"is":[3,38,70,97],"a":[4,9,24,51,65,105],"promising":[5],"technology":[6],"to":[7,44,64,72,126],"accommodate":[8],"large":[10],"design":[11],"in":[12,23,143],"one":[13,47],"chip,":[15],"but":[16,120],"the":[17,33,80,90,116,123,140],"limited":[18],"number":[19],"of":[20,83,93],"inter-die":[21],"connections":[22],"may":[27],"cause":[28],"routing":[29,48],"failures.":[30],"To":[31],"resolve":[32],"failures,":[34],"input/output":[35],"time-division":[36],"multiplexing":[37],"adopted":[39],"by":[40],"grouping":[41,58,78,86,109],"cross-die":[42,145],"signals":[43,59],"go":[45],"through":[46],"channel":[49],"with":[50],"timing":[52,147],"penalty":[53],"after":[54,60],"netlist":[55],"partitioning.":[56],"However,":[57],"partitioning":[61,75,84,107,130],"might":[62],"lead":[63],"suboptimal":[66],"solution.":[67],"Consequently,":[68],"it":[69],"desirable":[71],"consider":[73],"simultaneous":[74,95,106],"and":[76,85,89,108,149],"signal":[77,146],"although":[79],"optimization":[81,96],"objectives":[82,118],"are":[87],"different,":[88],"time":[91,124,128],"complexity":[92,125],"such":[94],"usually":[98],"high.":[99],"In":[100],"this":[101],"paper,":[102],"we":[103],"propose":[104],"algorithm":[110,138],"that":[111,135],"can":[112],"not":[113],"only":[114],"integrate":[115],"two":[117],"smoothly,":[119],"also":[121],"reduce":[122],"linear":[127],"per":[129],"iteration.":[131],"Experimental":[132],"results":[133],"show":[134],"our":[136],"proposed":[137],"outperforms":[139],"state-of-the-arts":[141],"flow":[142],"both":[144],"criticality":[148],"system-clock":[150],"periods.":[151]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":2}],"updated_date":"2026-03-12T08:34:05.389933","created_date":"2025-10-10T00:00:00"}