{"id":"https://openalex.org/W2906795937","doi":"https://doi.org/10.1145/3240302.3240429","title":"Opportunistic compression for direct-mapped DRAM caches","display_name":"Opportunistic compression for direct-mapped DRAM caches","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2906795937","doi":"https://doi.org/10.1145/3240302.3240429","mag":"2906795937"},"language":"en","primary_location":{"id":"doi:10.1145/3240302.3240429","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240302.3240429","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072086494","display_name":"Alaa R. Alameldeen","orcid":"https://orcid.org/0000-0002-9064-4621"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alaa R. Alameldeen","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112016404","display_name":"Rajat Agarwal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Rajat Agarwal","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":1.1015,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.75805698,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"136"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8751609921455383},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7452167868614197},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5177344679832458},{"id":"https://openalex.org/keywords/compression","display_name":"Compression (physics)","score":0.4910297393798828},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.49072039127349854},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46555453538894653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4591725170612335},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.4401406943798065},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2510775327682495},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07651197910308838}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8751609921455383},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7452167868614197},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5177344679832458},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.4910297393798828},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.49072039127349854},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46555453538894653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4591725170612335},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4401406943798065},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2510775327682495},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07651197910308838},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3240302.3240429","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240302.3240429","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.7699999809265137,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1963881655","https://openalex.org/W1976494130","https://openalex.org/W1976919080","https://openalex.org/W1979978831","https://openalex.org/W1983305800","https://openalex.org/W1995287338","https://openalex.org/W2082982763","https://openalex.org/W2093819294","https://openalex.org/W2095872092","https://openalex.org/W2101756288","https://openalex.org/W2114668191","https://openalex.org/W2116674125","https://openalex.org/W2120829734","https://openalex.org/W2123488428","https://openalex.org/W2130252115","https://openalex.org/W2131926352","https://openalex.org/W2134784745","https://openalex.org/W2147657598","https://openalex.org/W2148797773","https://openalex.org/W2162752393","https://openalex.org/W2169865228","https://openalex.org/W2293682522","https://openalex.org/W2510275156","https://openalex.org/W2566158619","https://openalex.org/W2730965233","https://openalex.org/W4233785673","https://openalex.org/W4240589281","https://openalex.org/W6697337972","https://openalex.org/W7061618721"],"related_works":["https://openalex.org/W1571368810","https://openalex.org/W1796231360","https://openalex.org/W1616582327","https://openalex.org/W1784146144","https://openalex.org/W2379400621","https://openalex.org/W2372170743","https://openalex.org/W1558545464","https://openalex.org/W1579918296","https://openalex.org/W1484089092","https://openalex.org/W2908886010"],"abstract_inverted_index":{"Large":[0],"off-chip":[1,22],"DRAM":[2,33,53],"caches":[3,20],"offer":[4],"performance":[5],"and":[6,21,37,44],"bandwidth":[7],"improvements":[8],"for":[9,35],"many":[10],"systems":[11],"by":[12],"bridging":[13],"the":[14,26,56],"gap":[15],"between":[16],"on-chip":[17],"last":[18],"level":[19],"memories.":[23],"To":[24],"avoid":[25],"high":[27],"hit":[28,60],"latency":[29,61],"resulting":[30],"from":[31,64],"serial":[32],"accesses":[34],"tags":[36,43],"data,":[38],"prior":[39],"work":[40],"proposed":[41],"co-locating":[42],"data":[45],"to":[46,69],"be":[47],"accessed":[48],"together.":[49],"The":[50],"state-of-the-art":[51],"block-based":[52],"cache":[54],"design,":[55],"Alloy":[57],"Cache,":[58],"reduces":[59],"but":[62],"suffers":[63],"increased":[65],"miss":[66],"rate":[67],"due":[68],"its":[70],"direct-mapped":[71],"design.":[72]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}