{"id":"https://openalex.org/W2908077141","doi":"https://doi.org/10.1145/3240302.3240317","title":"Main memory latency simulation","display_name":"Main memory latency simulation","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2908077141","doi":"https://doi.org/10.1145/3240302.3240317","mag":"2908077141"},"language":"en","primary_location":{"id":"doi:10.1145/3240302.3240317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240302.3240317","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://upcommons.upc.edu/bitstream/2117/190438/3/Sanchez%20et%20al.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061500663","display_name":"Rommel S\u00e1nchez Verdejo","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Rommel S\u00e1nchez Verdejo","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014340343","display_name":"Kazi Asifuzzaman","orcid":"https://orcid.org/0000-0002-4004-4791"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Kazi Asifuzzaman","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084238114","display_name":"Milan Radulovic","orcid":"https://orcid.org/0000-0001-9244-743X"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Milan Radulovic","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021600526","display_name":"Petar Radojkovi\u0107","orcid":"https://orcid.org/0000-0002-9334-3330"},"institutions":[{"id":"https://openalex.org/I2799803557","display_name":"Barcelona Supercomputing Center","ror":"https://ror.org/05sd8tv96","country_code":"ES","type":"facility","lineage":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]},{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Petar Radojkovi\u0107","raw_affiliation_strings":["Barcelona Supercomputing Center (BSC), Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Barcelona Supercomputing Center (BSC), Barcelona, Spain","institution_ids":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075755125","display_name":"Eduard Ayguad\u00e9","orcid":"https://orcid.org/0000-0002-5146-103X"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Eduard Ayguad\u00e9","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047597896","display_name":"Bruce Jacob","orcid":"https://orcid.org/0009-0005-3493-8245"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bruce Jacob","raw_affiliation_strings":["University of Maryland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1014,"has_fulltext":true,"cited_by_count":10,"citation_normalized_percentile":{"value":0.7596356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"107","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8142331838607788},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5689018964767456},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5543399453163147},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5288447141647339},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5142288208007812},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5141823291778564},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4846497178077698},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4822881519794464},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.47198373079299927},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4711509943008423},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.46019816398620605},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.45755353569984436},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.44565677642822266},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.42532479763031006},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.42422306537628174},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.39676710963249207},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.39191994071006775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3861183226108551},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38028910756111145},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.3084295988082886},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.2991182208061218},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28606367111206055},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.28141990303993225},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2590183913707733},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07440048456192017}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8142331838607788},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5689018964767456},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5543399453163147},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5288447141647339},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5142288208007812},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5141823291778564},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4846497178077698},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4822881519794464},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.47198373079299927},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4711509943008423},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.46019816398620605},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.45755353569984436},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.44565677642822266},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.42532479763031006},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.42422306537628174},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.39676710963249207},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.39191994071006775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3861183226108551},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38028910756111145},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.3084295988082886},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.2991182208061218},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28606367111206055},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.28141990303993225},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2590183913707733},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07440048456192017},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3240302.3240317","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3240302.3240317","pdf_url":null,"source":{"id":"https://openalex.org/S4306524191","display_name":"Proceedings of the International Symposium on Memory Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the International Symposium on Memory Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:upcommons.upc.edu:2117/190438","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/190438","pdf_url":"https://upcommons.upc.edu/bitstream/2117/190438/3/Sanchez%20et%20al.pdf","source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference report"}],"best_oa_location":{"id":"pmh:oai:upcommons.upc.edu:2117/190438","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/190438","pdf_url":"https://upcommons.upc.edu/bitstream/2117/190438/3/Sanchez%20et%20al.pdf","source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference report"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2436365243","display_name":null,"funder_award_id":"2014-SGR-1051","funder_id":"https://openalex.org/F4320321505","funder_display_name":"Generalitat de Catalunya"},{"id":"https://openalex.org/G4496054538","display_name":null,"funder_award_id":"SEV-2015-0493","funder_id":"https://openalex.org/F4320323737","funder_display_name":"Ministerio de Ciencia y Tecnolog\u00eda"},{"id":"https://openalex.org/G5947849998","display_name":null,"funder_award_id":"TIN2015\u201065316\u2010P","funder_id":"https://openalex.org/F4320323737","funder_display_name":"Ministerio de Ciencia y Tecnolog\u00eda"},{"id":"https://openalex.org/G7096924396","display_name":null,"funder_award_id":"TIN2015-65316","funder_id":"https://openalex.org/F4320321505","funder_display_name":"Generalitat de Catalunya"},{"id":"https://openalex.org/G7291222407","display_name":null,"funder_award_id":"TIN2015-65316","funder_id":"https://openalex.org/F4320323737","funder_display_name":"Ministerio de Ciencia y Tecnolog\u00eda"},{"id":"https://openalex.org/G893344584","display_name":null,"funder_award_id":"2014-SGR- 1272","funder_id":"https://openalex.org/F4320321505","funder_display_name":"Generalitat de Catalunya"}],"funders":[{"id":"https://openalex.org/F4320321505","display_name":"Generalitat de Catalunya","ror":"https://ror.org/01bg62x04"},{"id":"https://openalex.org/F4320323737","display_name":"Ministerio de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/034900433"},{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2908077141.pdf","grobid_xml":"https://content.openalex.org/works/W2908077141.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W2013062050","https://openalex.org/W2034062945","https://openalex.org/W2034861439","https://openalex.org/W2036853599","https://openalex.org/W2041420601","https://openalex.org/W2044206819","https://openalex.org/W2105321788","https://openalex.org/W2113235308","https://openalex.org/W2119296805","https://openalex.org/W2123306627","https://openalex.org/W2125786790","https://openalex.org/W2143823686","https://openalex.org/W2145021036","https://openalex.org/W2147657366","https://openalex.org/W2149075075","https://openalex.org/W2161522487","https://openalex.org/W2162639668","https://openalex.org/W2164264749","https://openalex.org/W2169875292","https://openalex.org/W2296602564","https://openalex.org/W2754369244"],"related_works":["https://openalex.org/W4321458411","https://openalex.org/W3108993429","https://openalex.org/W2782503170","https://openalex.org/W2168550483","https://openalex.org/W2047684617","https://openalex.org/W4281924108","https://openalex.org/W2041174925","https://openalex.org/W2316890442","https://openalex.org/W2117533242","https://openalex.org/W4233816696"],"abstract_inverted_index":{"The":[0],"community":[1],"accepted":[2],"the":[3,13,20,40,43,48],"need":[4],"for":[5],"a":[6,33],"detailed":[7],"simulation":[8],"of":[9,39],"main":[10,22],"memory.":[11],"Currently,":[12],"CPU":[14,27],"simulators":[15,30],"are":[16],"usually":[17],"coupled":[18],"with":[19],"cycle-accurate":[21],"memory":[23,29,49],"simulators.":[24],"However,":[25],"coupling":[26],"and":[28,47,55],"is":[31],"not":[32,57],"straight-forward":[34],"task":[35],"because":[36],"some":[37],"pieces":[38],"circuitry":[41],"between":[42],"last":[44],"level":[45],"cache":[46],"DIMMs":[50],"could":[51],"be":[52],"easily":[53],"overlooked":[54],"therefore":[56],"accounted":[58],"for.":[59]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":4}],"updated_date":"2026-08-02T14:50:37.381335","created_date":"2025-10-10T00:00:00"}