{"id":"https://openalex.org/W2809409253","doi":"https://doi.org/10.1145/3229762.3229766","title":"Leveraging the VTA-TVM Hardware-Software Stack for FPGA Acceleration of 8-bit ResNet-18 Inference","display_name":"Leveraging the VTA-TVM Hardware-Software Stack for FPGA Acceleration of 8-bit ResNet-18 Inference","publication_year":2018,"publication_date":"2018-06-20","ids":{"openalex":"https://openalex.org/W2809409253","doi":"https://doi.org/10.1145/3229762.3229766","mag":"2809409253"},"language":"en","primary_location":{"id":"doi:10.1145/3229762.3229766","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3229762.3229766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103206590","display_name":"Thierry Moreau","orcid":"https://orcid.org/0000-0002-5257-4044"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Thierry Moreau","raw_affiliation_strings":["University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101471083","display_name":"Tianqi Chen","orcid":"https://orcid.org/0000-0002-2336-1875"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tianqi Chen","raw_affiliation_strings":["University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081914923","display_name":"Lu\u00eds Ceze","orcid":"https://orcid.org/0000-0002-1377-6217"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luis Ceze","raw_affiliation_strings":["University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8423740863800049},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7679232954978943},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.735970139503479},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6301394104957581},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5366852283477783},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5041490793228149},{"id":"https://openalex.org/keywords/deep-learning","display_name":"Deep learning","score":0.4943411350250244},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4918375015258789},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4789507985115051},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.4745020568370819},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37745797634124756},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17106616497039795},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15321490168571472}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8423740863800049},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7679232954978943},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.735970139503479},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6301394104957581},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5366852283477783},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5041490793228149},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.4943411350250244},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4918375015258789},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4789507985115051},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.4745020568370819},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37745797634124756},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17106616497039795},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15321490168571472}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3229762.3229766","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3229762.3229766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2154790323","https://openalex.org/W2186615578","https://openalex.org/W2606722458","https://openalex.org/W2784957519","https://openalex.org/W2787513823"],"related_works":["https://openalex.org/W3096456556","https://openalex.org/W4240253816","https://openalex.org/W2169584677","https://openalex.org/W2979513934","https://openalex.org/W4232954277","https://openalex.org/W2020341030","https://openalex.org/W2749133591","https://openalex.org/W2367473450","https://openalex.org/W2518118925","https://openalex.org/W3159273459"],"abstract_inverted_index":{"We":[0],"present":[1,43],"a":[2,51,63,77,82],"full-stack":[3],"design":[4],"to":[5,33,72,102],"accelerate":[6],"deep":[7,27],"learning":[8,28],"inference":[9,75],"with":[10],"FPGAs.":[11],"Our":[12,60,90],"contribution":[13],"is":[14],"two-fold.":[15],"At":[16,37],"the":[17,25,38,39,44,100],"software":[18],"layer,":[19,41],"we":[20,42],"leverage":[21],"and":[22,54,68,104],"extend":[23],"TVM,":[24],"end-to-end":[26],"optimizing":[29],"compiler,":[30],"in":[31,66],"order":[32],"harness":[34],"FPGA-based":[35],"acceleration.":[36],"hardware":[40,92],"Versatile":[45],"Tensor":[46],"Accelerator":[47],"(VTA)":[48],"which":[49],"presents":[50],"generic,":[52],"modular,":[53],"customizable":[55],"architecture":[56],"for":[57,99],"TPU-like":[58],"accelerators.":[59],"results":[61],"take":[62],"ResNet-18":[64],"description":[65],"MxNet":[67],"compiles":[69],"it":[70],"down":[71],"perform":[73],"8-bit":[74],"on":[76,81],"256-PE":[78],"accelerator":[79],"implemented":[80],"low-cost":[83],"Xilinx":[84],"Zynq":[85],"FPGA,":[86],"clocked":[87],"at":[88,107],"100MHz.":[89],"full":[91],"acceleration":[93],"stack":[94],"will":[95],"be":[96],"made":[97],"available":[98],"community":[101],"reproduce,":[103],"build":[105],"upon":[106],"http://github.com/uwsaml/vta.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":4},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}