{"id":"https://openalex.org/W2803317929","doi":"https://doi.org/10.1145/3214292.3214296","title":"An MLP-aware leakage-free memory controller","display_name":"An MLP-aware leakage-free memory controller","publication_year":2018,"publication_date":"2018-05-25","ids":{"openalex":"https://openalex.org/W2803317929","doi":"https://doi.org/10.1145/3214292.3214296","mag":"2803317929"},"language":"en","primary_location":{"id":"doi:10.1145/3214292.3214296","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3214292.3214296","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3214292.3214296","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3214292.3214296","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014354212","display_name":"Andrew Vuong","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew Vuong","raw_affiliation_strings":["University of Utah, Salt Lake City, Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067008084","display_name":"Ali Shafiee","orcid":"https://orcid.org/0000-0001-7154-9138"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ali Shafiee","raw_affiliation_strings":["University of Utah, Salt Lake City, Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066764886","display_name":"Meysam Taassori","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Meysam Taassori","raw_affiliation_strings":["University of Utah, Salt Lake City, Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087056095","display_name":"Rajeev Balasubramonian","orcid":"https://orcid.org/0009-0009-4093-5904"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajeev Balasubramonian","raw_affiliation_strings":["University of Utah, Salt Lake City, Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, Utah","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":0.5069,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.73169737,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9883999824523926,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8174128532409668},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7955690622329712},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5626869797706604},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4916103482246399},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4890194833278656},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4738350808620453},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.41944801807403564},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4185267984867096},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37200623750686646},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3447645902633667},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2930111885070801},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2474917471408844}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8174128532409668},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7955690622329712},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5626869797706604},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4916103482246399},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4890194833278656},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4738350808620453},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.41944801807403564},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4185267984867096},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37200623750686646},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3447645902633667},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2930111885070801},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2474917471408844},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3214292.3214296","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3214292.3214296","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3214292.3214296","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3214292.3214296","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3214292.3214296","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3214292.3214296","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy","raw_type":"proceedings-article"},"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[{"id":"https://openalex.org/G1872755561","display_name":"SaTC: CORE: Small: Efficient Hardware-Aware and Hardware-Enabled Algorithms for Secure In-Memory Databases","funder_award_id":"1718834","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G3101893888","display_name":null,"funder_award_id":"CNS-1718834","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G4926700023","display_name":"CSR: Medium: Energy-Efficient Architectures for Emerging Big-Data Workloads","funder_award_id":"1302663","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G7134038885","display_name":"CSR: Small: Adaptive Brink-of-Failure Memory Architectures for Future Technologies and Workloads","funder_award_id":"1423583","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2803317929.pdf","grobid_xml":"https://content.openalex.org/works/W2803317929.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W2017371166","https://openalex.org/W2092160538","https://openalex.org/W2106728965","https://openalex.org/W2119028650","https://openalex.org/W2129513794","https://openalex.org/W2151917022","https://openalex.org/W2165697076","https://openalex.org/W2166293920","https://openalex.org/W2239632431","https://openalex.org/W2612480636","https://openalex.org/W2781723315","https://openalex.org/W2791034507"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2185658074","https://openalex.org/W2896161911","https://openalex.org/W4285245242","https://openalex.org/W2907559171","https://openalex.org/W2019238062","https://openalex.org/W2138825797","https://openalex.org/W4243618206","https://openalex.org/W4393076761","https://openalex.org/W1725472669"],"abstract_inverted_index":{"Timing":[0],"channels":[1,20],"can":[2,32],"be":[3,34],"exploited":[4],"to":[5,36,72],"leak":[6],"information":[7],"between":[8],"two":[9],"virtual":[10],"machines":[11],"running":[12],"on":[13],"a":[14,38],"shared":[15,29],"server.":[16],"Indeed,":[17],"cache":[18],"timing":[19,39,50,98],"are":[21],"important":[22],"components":[23],"in":[24],"the":[25,63,68,73,86,89],"Spectre":[26],"attack.":[27],"A":[28],"memory":[30,45,69,82,96],"controller":[31,70,83,97],"also":[33],"leveraged":[35],"establish":[37],"channel.":[40],"Recent":[41],"efforts":[42],"have":[43],"designed":[44],"controllers":[46],"that":[47,53],"eliminate":[48],"such":[49],"channels,":[51],"but":[52],"incur":[54],"throughput":[55],"penalties":[56],"of":[57,77,88],"over":[58],"2X.":[59],"This":[60],"paper":[61],"advances":[62],"state-of-the-art":[64,90],"by":[65,92],"better":[66],"matching":[67],"policies":[71],"memory-level-parallelism":[74],"(MLP)":[75],"needs":[76],"typical":[78],"applications.":[79],"Our":[80],"new":[81],"improves":[84],"upon":[85],"performance":[87],"policy":[91],"14%,":[93],"while":[94],"eliminating":[95],"channels.":[99]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}