{"id":"https://openalex.org/W2805643271","doi":"https://doi.org/10.1145/3211922.3211931","title":"Efficient compute node-local replication mechanisms for NVRAM-centric data structures","display_name":"Efficient compute node-local replication mechanisms for NVRAM-centric data structures","publication_year":2018,"publication_date":"2018-06-05","ids":{"openalex":"https://openalex.org/W2805643271","doi":"https://doi.org/10.1145/3211922.3211931","mag":"2805643271"},"language":"en","primary_location":{"id":"doi:10.1145/3211922.3211931","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3211922.3211931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th International Workshop on Data Management on New Hardware","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://tud.qucosa.de/api/qucosa%3A79868/attachment/ATT-0/","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015311644","display_name":"Mikhail Zarubin","orcid":"https://orcid.org/0000-0001-5692-5780"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Mikhail Zarubin","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086097318","display_name":"Thomas Kissinger","orcid":"https://orcid.org/0000-0002-6680-1295"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thomas Kissinger","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057703543","display_name":"Dirk Habich","orcid":"https://orcid.org/0000-0002-8671-5466"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dirk Habich","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063512642","display_name":"Wolfgang Lehner","orcid":"https://orcid.org/0000-0001-8107-2775"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Lehner","raw_affiliation_strings":["Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5015311644"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.9771,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.78591975,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.8640776872634888},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7734094858169556},{"id":"https://openalex.org/keywords/replication","display_name":"Replication (statistics)","score":0.7575362920761108},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6749635934829712},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5410787463188171},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4994018077850342},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41855162382125854},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.377395898103714},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3280901312828064},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2954000234603882},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.177891343832016},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1377238631248474},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.12935352325439453},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.10790959000587463},{"id":"https://openalex.org/keywords/biology","display_name":"Biology","score":0.07979258894920349}],"concepts":[{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.8640776872634888},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7734094858169556},{"id":"https://openalex.org/C12590798","wikidata":"https://www.wikidata.org/wiki/Q3933199","display_name":"Replication (statistics)","level":2,"score":0.7575362920761108},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6749635934829712},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5410787463188171},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4994018077850342},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41855162382125854},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.377395898103714},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3280901312828064},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2954000234603882},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.177891343832016},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1377238631248474},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.12935352325439453},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.10790959000587463},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.07979258894920349},{"id":"https://openalex.org/C159047783","wikidata":"https://www.wikidata.org/wiki/Q7215","display_name":"Virology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3211922.3211931","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3211922.3211931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 14th International Workshop on Data Management on New Hardware","raw_type":"proceedings-article"},{"id":"pmh:oai:qucosa:de:qucosa:79868","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A79868","pdf_url":"https://tud.qucosa.de/api/qucosa%3A79868/attachment/ATT-0/","source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"}],"best_oa_location":{"id":"pmh:oai:qucosa:de:qucosa:79868","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A79868","pdf_url":"https://tud.qucosa.de/api/qucosa%3A79868/attachment/ATT-0/","source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2060274946","display_name":null,"funder_award_id":"HAEC)","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G5519651083","display_name":null,"funder_award_id":"16/27-1","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G6052429835","display_name":null,"funder_award_id":"(DFG)","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G6699961224","display_name":null,"funder_award_id":"LE-1416/27-1","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G7002107308","display_name":null,"funder_award_id":"CRC 912","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2805643271.pdf"},"referenced_works_count":25,"referenced_works":["https://openalex.org/W1422898865","https://openalex.org/W1567210335","https://openalex.org/W2000345607","https://openalex.org/W2015194563","https://openalex.org/W2051068509","https://openalex.org/W2090204040","https://openalex.org/W2117169958","https://openalex.org/W2130301020","https://openalex.org/W2164999122","https://openalex.org/W2290022288","https://openalex.org/W2396406070","https://openalex.org/W2404397702","https://openalex.org/W2414992661","https://openalex.org/W2433709474","https://openalex.org/W2488102770","https://openalex.org/W2531719112","https://openalex.org/W2538785949","https://openalex.org/W2578260324","https://openalex.org/W2612480576","https://openalex.org/W2614073040","https://openalex.org/W2752849758","https://openalex.org/W2790463284","https://openalex.org/W2798607736","https://openalex.org/W2907174891","https://openalex.org/W4251162132"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W2098207691","https://openalex.org/W3148568549","https://openalex.org/W1648516568","https://openalex.org/W361036515","https://openalex.org/W2800626838","https://openalex.org/W2169710001","https://openalex.org/W2347426858","https://openalex.org/W2542548909","https://openalex.org/W2110995678"],"abstract_inverted_index":{"Non-volatile":[0],"random-access":[1],"memory":[2,116],"(NVRAM)":[3],"is":[4],"about":[5],"to":[6,15,42,45,50,74,97,107],"hit":[7],"the":[8,16,30,36,76,108,113],"market":[9],"and":[10,49,69,88],"will":[11,28],"require":[12],"significant":[13],"changes":[14],"architecture":[17],"of":[18,56,112],"in-memory":[19],"database":[20,26],"systems.":[21],"Since":[22],"such":[23],"hybrid":[24],"DRAM-NVRAM":[25],"systems":[27],"keep":[29],"primary":[31],"data":[32,47],"solely":[33],"persistent":[34,115],"in":[35,54],"NVRAM,":[37],"efficient":[38,81],"replication":[39,67,83,104,110],"mechanisms":[40,73,105],"need":[41],"be":[43],"considered":[44],"prevent":[46],"losses":[48],"guarantee":[51],"high":[52],"availability":[53],"case":[55],"NVDIMM":[57],"failures.":[58],"In":[59],"this":[60],"paper,":[61],"we":[62,94],"argue":[63],"for":[64,79,101],"a":[65,85],"software-based":[66],"approach":[68],"present":[70],"compute":[71],"node-local":[72],"provide":[75],"building":[77],"blocks":[78],"an":[80],"NVRAM":[82],"with":[84],"low":[86],"latency":[87],"throughput":[89],"penalty.":[90],"Within":[91],"our":[92,102],"evaluation,":[93],"measured":[95],"up":[96],"10x":[98],"less":[99],"overhead":[100],"optimized":[103],"compared":[106],"basic":[109],"mechanism":[111],"Intel":[114],"development":[117],"kit":[118],"(PMDK).":[119]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}