{"id":"https://openalex.org/W2808997409","doi":"https://doi.org/10.1145/3210377.3210657","title":"Brief Announcement","display_name":"Brief Announcement","publication_year":2018,"publication_date":"2018-07-11","ids":{"openalex":"https://openalex.org/W2808997409","doi":"https://doi.org/10.1145/3210377.3210657","mag":"2808997409"},"language":"en","primary_location":{"id":"doi:10.1145/3210377.3210657","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3210377.3210657","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3210377.3210657","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3210377.3210657","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067109059","display_name":"Alvaro Velasquez","orcid":"https://orcid.org/0000-0001-6757-105X"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alvaro Velasquez","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075978538","display_name":"Sumit Kumar Jha","orcid":"https://orcid.org/0000-0003-0354-2940"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumit Kumar Jha","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5067109059"],"corresponding_institution_ids":["https://openalex.org/I106165777"],"apc_list":null,"apc_paid":null,"fwci":0.6543,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":{"value":0.7099149,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"95","last_page":"98"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.8386690616607666},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7570743560791016},{"id":"https://openalex.org/keywords/transitive-closure","display_name":"Transitive closure","score":0.7064175605773926},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6218013167381287},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.5302331447601318},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4724745452404022},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4719010293483734},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.43082961440086365},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3544795513153076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2947356700897217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2944590449333191},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.27357420325279236},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.1910293698310852},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13569089770317078},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11207649111747742},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0735708475112915},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06840941309928894}],"concepts":[{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.8386690616607666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7570743560791016},{"id":"https://openalex.org/C128896722","wikidata":"https://www.wikidata.org/wiki/Q1501387","display_name":"Transitive closure","level":2,"score":0.7064175605773926},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6218013167381287},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.5302331447601318},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4724745452404022},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4719010293483734},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.43082961440086365},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3544795513153076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2947356700897217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2944590449333191},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.27357420325279236},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.1910293698310852},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13569089770317078},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11207649111747742},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0735708475112915},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06840941309928894},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3210377.3210657","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3210377.3210657","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3210377.3210657","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures","raw_type":"proceedings-article"},{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-11583","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/10584","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1145/3210377.3210657","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3210377.3210657","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3210377.3210657","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1523888516","display_name":null,"funder_award_id":"FA9550-","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G207856546","display_name":null,"funder_award_id":"FA9550-16-1-025","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G230078430","display_name":null,"funder_award_id":"FA9550-16","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G3392305090","display_name":null,"funder_award_id":"-16-1-","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G3616359867","display_name":null,"funder_award_id":"FA9550-16-1","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G5809100787","display_name":null,"funder_award_id":"FA9550","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G6858777407","display_name":null,"funder_award_id":"FA9550-16-1-0255","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"},{"id":"https://openalex.org/G7090116110","display_name":null,"funder_award_id":"FA9550","funder_id":"https://openalex.org/F4320332467","funder_display_name":"U.S. Air Force"},{"id":"https://openalex.org/G8521281903","display_name":null,"funder_award_id":"AFOSR","funder_id":"https://openalex.org/F4320332467","funder_display_name":"U.S. Air Force"},{"id":"https://openalex.org/G8971503227","display_name":null,"funder_award_id":"FA9550-16-1-0255.","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332467","display_name":"U.S. Air Force","ror":"https://ror.org/006gmme17"},{"id":"https://openalex.org/F4320338279","display_name":"Air Force Office of Scientific Research","ror":"https://ror.org/011e9bt93"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2808997409.pdf","grobid_xml":"https://content.openalex.org/works/W2808997409.grobid-xml"},"referenced_works_count":20,"referenced_works":["https://openalex.org/W1509843845","https://openalex.org/W1554230273","https://openalex.org/W1861590051","https://openalex.org/W2008620264","https://openalex.org/W2018761720","https://openalex.org/W2047505657","https://openalex.org/W2061118827","https://openalex.org/W2089857781","https://openalex.org/W2104085672","https://openalex.org/W2154541546","https://openalex.org/W2163031927","https://openalex.org/W2169015768","https://openalex.org/W2184708688","https://openalex.org/W2511469654","https://openalex.org/W2526202524","https://openalex.org/W2608368043","https://openalex.org/W2736515622","https://openalex.org/W2742513757","https://openalex.org/W2769133055","https://openalex.org/W4239545644"],"related_works":["https://openalex.org/W2334181344","https://openalex.org/W2143690511","https://openalex.org/W4281569059","https://openalex.org/W1609765068","https://openalex.org/W2770431327","https://openalex.org/W4381612949","https://openalex.org/W1975698617","https://openalex.org/W4389476357","https://openalex.org/W4385831250","https://openalex.org/W2561005478"],"abstract_inverted_index":{"The":[0,32],"infamous":[1],"memory-processor":[2],"bottleneck":[3],"has":[4],"motivated":[5],"the":[6,17],"search":[7],"for":[8],"logic-in-memory":[9],"architectures.":[10],"In":[11],"this":[12],"paper,":[13],"we":[14],"demonstrate":[15],"how":[16],"transitive":[18],"closure":[19],"problem":[20],"can":[21],"be":[22],"solved":[23],"through":[24],"in-memory":[25],"computing":[26],"within":[27],"a":[28],"3D":[29],"crosspoint":[30],"memory.":[31],"proposed":[33],"architecture":[34],"requires":[35],"only":[36],"two":[37],"layers":[38],"of":[39],"1-diode":[40],"1-resistor":[41],"(1D1R)":[42],"interconnects":[43],"and":[44],"external":[45],"feedback":[46],"loops.":[47]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2018-06-29T00:00:00"}