{"id":"https://openalex.org/W2804404130","doi":"https://doi.org/10.1145/3200921.3204479","title":"Runtime Aware Architectures","display_name":"Runtime Aware Architectures","publication_year":2018,"publication_date":"2018-05-14","ids":{"openalex":"https://openalex.org/W2804404130","doi":"https://doi.org/10.1145/3200921.3204479","mag":"2804404130"},"language":"en","primary_location":{"id":"doi:10.1145/3200921.3204479","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3200921.3204479","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068170397","display_name":"Mateo Valero Cort\u00e9s","orcid":null},"institutions":[{"id":"https://openalex.org/I2799803557","display_name":"Barcelona Supercomputing Center","ror":"https://ror.org/05sd8tv96","country_code":"ES","type":"facility","lineage":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]},{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Mateo Valero Cortes","raw_affiliation_strings":["Barcelona Supercomputing Center &University of Catalonia, Barcelona, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Barcelona Supercomputing Center &University of Catalonia, Barcelona, Spain","institution_ids":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5068170397"],"corresponding_institution_ids":["https://openalex.org/I2799803557","https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03573097,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"3","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.850037693977356},{"id":"https://openalex.org/keywords/runtime-system","display_name":"Runtime system","score":0.6829021573066711},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5289195775985718},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.45068612694740295},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44959771633148193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.441177099943161},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.41153624653816223},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35871344804763794}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.850037693977356},{"id":"https://openalex.org/C2780870223","wikidata":"https://www.wikidata.org/wiki/Q1004415","display_name":"Runtime system","level":2,"score":0.6829021573066711},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5289195775985718},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.45068612694740295},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44959771633148193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.441177099943161},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.41153624653816223},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35871344804763794},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3200921.3204479","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3200921.3204479","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W17155033","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W4312814274","https://openalex.org/W1590307681","https://openalex.org/W2536018345","https://openalex.org/W4285370786","https://openalex.org/W1996306926","https://openalex.org/W3023876411","https://openalex.org/W123152114"],"abstract_inverted_index":{"In":[0,139],"the":[1,4,9,15,19,26,33,56,91,116,126,133,157,164,166,180,187,190,198,211,220,234,237,241],"last":[2],"years":[3],"traditional":[5],"ways":[6],"to":[7,14,37,64,89,111,115,120,131,174,185,197,203,224],"keep":[8],"increase":[10],"of":[11,101,135,189,219,230,236,243],"hardware":[12,28,231],"performance":[13,188,205],"rate":[16],"predicted":[17],"by":[18,193,206],"Moore's":[20],"Law":[21],"vanished.":[22],"When":[23],"uni-cores":[24],"were":[25],"norm,":[27],"design":[29,134],"was":[30],"decoupled":[31],"from":[32,156],"software":[34],"stack":[35],"thanks":[36],"a":[38,82,147,151,216],"well":[39],"defined":[40],"Instruction":[41],"Set":[42],"Architecture":[43,149],"(ISA).":[44],"This":[45],"simple":[46,78],"interface":[47],"allowed":[48],"developing":[49],"applications":[50],"without":[51],"worrying":[52],"too":[53],"much":[54],"about":[55],"underlying":[57],"hardware,":[58],"while":[59],"computer":[60],"architects":[61],"proposed":[62],"techniques":[63],"aggressively":[65],"exploit":[66],"Instruction-Level":[67],"Parallelism":[68],"(ILP)":[69],"in":[70,99,170,240],"superscalar":[71],"processors.":[72],"Current":[73],"multi-cores":[74,137],"are":[75,87],"designed":[76,155],"as":[77],"symmetric":[79],"multiprocessors":[80],"on":[81],"chip.":[83],"While":[84],"these":[85],"designs":[86],"able":[88],"compensate":[90],"clock":[92],"frequency":[93],"stagnation,":[94],"they":[95],"face":[96],"multiple":[97],"problems":[98,221],"terms":[100],"power":[102],"consumption,":[103],"programmability,":[104],"resilience":[105],"or":[106],"memory.":[107],"The":[108,128],"solution":[109],"is":[110],"give":[112,215],"more":[113],"responsibility":[114],"runtime":[117,129,168,199,238],"system":[118,169,200,239],"and":[119,178,226],"let":[121],"it":[122,182],"tightly":[123],"collaborate":[124],"with":[125],"hardware.":[127],"has":[130],"drive":[132],"future":[136],"architectures.":[138],"this":[140],"talk,":[141,212],"we":[142,213],"introduce":[143],"an":[144],"approach":[145],"towards":[146],"Runtime-Aware":[148],"(RAA),":[150],"massively":[152],"parallel":[153,167],"architecture":[154],"runtime's":[158],"perspective.":[159],"RAA":[160,222],"aims":[161,223],"at":[162],"supporting":[163,233],"activity":[165,235],"three":[171],"ways:":[172],"First,":[173],"enable":[175],"fine-grain":[176],"tasking":[177],"support":[179],"opportunities":[181],"offers;":[183],"second,":[184],"improve":[186,204],"memory":[191],"subsystem":[192],"exposing":[194],"hybrid":[195],"hierarchies":[196],"and,":[201],"third,":[202],"using":[207],"vector":[208],"units.":[209],"During":[210],"will":[214],"general":[217],"overview":[218],"solve":[225],"provide":[227],"some":[228],"examples":[229],"components":[232],"context":[242],"multi-core":[244],"chips.":[245]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}