{"id":"https://openalex.org/W2808932028","doi":"https://doi.org/10.1145/3195970.3199846","title":"A modular digital VLSI flow for high-productivity SoC design","display_name":"A modular digital VLSI flow for high-productivity SoC design","publication_year":2018,"publication_date":"2018-06-19","ids":{"openalex":"https://openalex.org/W2808932028","doi":"https://doi.org/10.1145/3195970.3199846","mag":"2808932028"},"language":"en","primary_location":{"id":"doi:10.1145/3195970.3199846","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3199846","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010156116","display_name":"Brucek Khailany","orcid":"https://orcid.org/0000-0002-7584-3489"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Brucek Khailany","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082205505","display_name":"Evgeni Khmer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Evgeni Khmer","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045219356","display_name":"Rangharajan Venkatesan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rangharajan Venkatesan","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056153489","display_name":"Jason Clemons","orcid":"https://orcid.org/0000-0001-5533-417X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jason Clemons","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":null},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]},{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel S. Emer","raw_affiliation_strings":["NVIDIA and Massachusetts Institute of Technology"],"affiliations":[{"raw_affiliation_string":"NVIDIA and Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I4210127875","https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087082539","display_name":"Matthew Fojtik","orcid":"https://orcid.org/0000-0003-3138-9293"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Matthew Fojtik","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009735174","display_name":"Alicia Klinefelter","orcid":"https://orcid.org/0000-0002-0149-0393"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alicia Klinefelter","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009910914","display_name":"Michael Pellauer","orcid":"https://orcid.org/0000-0002-5305-4307"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michael Pellauer","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nathaniel Pinckney","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008683881","display_name":"Yakun Sophia Shao","orcid":"https://orcid.org/0000-0003-1811-5407"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yakun Sophia Shao","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078586017","display_name":"S Srinath","orcid":null},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shreesha Srinath","raw_affiliation_strings":["Cornell University"],"affiliations":[{"raw_affiliation_string":"Cornell University","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026966440","display_name":"Christopher Torng","orcid":"https://orcid.org/0000-0002-2385-619X"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher Torng","raw_affiliation_strings":["Cornell University"],"affiliations":[{"raw_affiliation_string":"Cornell University","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053699612","display_name":"Sam Likun Xi","orcid":null},"institutions":[{"id":"https://openalex.org/I2801851002","display_name":"Harvard University Press","ror":"https://ror.org/006v7bf86","country_code":"US","type":"other","lineage":["https://openalex.org/I136199984","https://openalex.org/I2801851002"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sam (Likun) Xi","raw_affiliation_strings":["Harvard University"],"affiliations":[{"raw_affiliation_string":"Harvard University","institution_ids":["https://openalex.org/I2801851002"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100612105","display_name":"Yanqing Zhang","orcid":"https://orcid.org/0000-0003-2349-1925"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yanqing Zhang","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042467215","display_name":"Brian Zimmer","orcid":"https://orcid.org/0000-0001-9997-3141"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Brian Zimmer","raw_affiliation_strings":["NVIDIA"],"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5010156116"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.0691,"has_fulltext":false,"cited_by_count":39,"citation_normalized_percentile":{"value":0.97665607,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8636949062347412},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7544313669204712},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.6965934038162231},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6920254230499268},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6895738840103149},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6831280589103699},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5758447051048279},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5479490756988525},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5211841464042664},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4206416606903076},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.10760703682899475},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08258664608001709},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06067880988121033}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8636949062347412},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7544313669204712},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.6965934038162231},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6920254230499268},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6895738840103149},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6831280589103699},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5758447051048279},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5479490756988525},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5211841464042664},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4206416606903076},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.10760703682899475},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08258664608001709},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06067880988121033}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3195970.3199846","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3199846","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"},{"id":"https://openalex.org/F4320309622","display_name":"Harvard University","ror":"https://ror.org/03vek6s52"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1951447215","https://openalex.org/W1983394510","https://openalex.org/W2035501710","https://openalex.org/W2060736133","https://openalex.org/W2079751107","https://openalex.org/W2100720925","https://openalex.org/W2134354173","https://openalex.org/W2402164368","https://openalex.org/W2529252381","https://openalex.org/W2757637133","https://openalex.org/W3023154643","https://openalex.org/W3100932218"],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W2242433395","https://openalex.org/W2544073398","https://openalex.org/W2548514518","https://openalex.org/W2579932084","https://openalex.org/W2379408401","https://openalex.org/W1996778651","https://openalex.org/W47369351","https://openalex.org/W1603163876","https://openalex.org/W2133642747"],"abstract_inverted_index":{"A":[0],"high-productivity":[1],"digital":[2],"VLSI":[3,29],"flow":[4,12,43],"for":[5],"designing":[6],"complex":[7],"SoCs":[8],"is":[9],"presented.":[10],"The":[11,42],"includes":[13],"high-level":[14],"synthesis":[15],"tools,":[16],"an":[17],"object-oriented":[18],"library":[19],"of":[20],"synthesizable":[21],"SystemC":[22],"and":[23,26,54],"C++":[24],"components,":[25],"a":[27,47],"modular":[28],"physical":[30],"design":[31],"approach":[32],"based":[33],"on":[34,46],"fine-grained":[35],"globally":[36],"asynchronous":[37],"locally":[38],"synchronous":[39],"(GALS)":[40],"clocking.":[41],"was":[44],"demonstrated":[45],"16nm":[48],"FinFET":[49],"testchip":[50],"targeting":[51],"machine":[52],"learning":[53],"computer":[55],"vision.":[56]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":11},{"year":2020,"cited_by_count":9},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}