{"id":"https://openalex.org/W2809524490","doi":"https://doi.org/10.1145/3195970.3196092","title":"PIMA-logic","display_name":"PIMA-logic","publication_year":2018,"publication_date":"2018-06-19","ids":{"openalex":"https://openalex.org/W2809524490","doi":"https://doi.org/10.1145/3195970.3196092","mag":"2809524490"},"language":"en","primary_location":{"id":"doi:10.1145/3195970.3196092","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3196092","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://stars.library.ucf.edu/scopus2015/7863","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051680668","display_name":"Shaahin Angizi","orcid":"https://orcid.org/0000-0003-2289-6381"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shaahin Angizi","raw_affiliation_strings":["University of Central Florida"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036755436","display_name":"Zhezhi He","orcid":"https://orcid.org/0000-0002-6357-236X"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhezhi He","raw_affiliation_strings":["University of Central Florida"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047916979","display_name":"Deliang Fan","orcid":"https://orcid.org/0000-0002-7989-6297"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deliang Fan","raw_affiliation_strings":["University of Central Florida"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I106165777"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6668265461921692},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5269753932952881},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.5048282742500305},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49092867970466614},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.48887890577316284},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48781540989875793},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.48305660486221313},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.45413124561309814},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44602975249290466},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42635542154312134},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3789713978767395},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33946913480758667},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.33905333280563354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3227608799934387},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29267171025276184},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.185116708278656},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14049533009529114},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.097606360912323},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.0970938503742218}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6668265461921692},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5269753932952881},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.5048282742500305},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49092867970466614},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.48887890577316284},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48781540989875793},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.48305660486221313},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.45413124561309814},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44602975249290466},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42635542154312134},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3789713978767395},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33946913480758667},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.33905333280563354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3227608799934387},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29267171025276184},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.185116708278656},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14049533009529114},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.097606360912323},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0970938503742218},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/3195970.3196092","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3196092","pdf_url":null,"source":null,"license":"public-domain","license_id":"https://openalex.org/licenses/public-domain","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-8862","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/7863","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-8862","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/7863","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"},"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W2010202670","https://openalex.org/W2096320918","https://openalex.org/W2102449048","https://openalex.org/W2113809410","https://openalex.org/W2114972738","https://openalex.org/W2134697089","https://openalex.org/W2138040286","https://openalex.org/W2147657366","https://openalex.org/W2162433640","https://openalex.org/W2170382128","https://openalex.org/W2214682759","https://openalex.org/W2396622873","https://openalex.org/W2416900089","https://openalex.org/W2505622901","https://openalex.org/W2518281301","https://openalex.org/W2584275485","https://openalex.org/W2584875058","https://openalex.org/W2588236721","https://openalex.org/W2613569094","https://openalex.org/W2615320339","https://openalex.org/W2623880136","https://openalex.org/W2738393257","https://openalex.org/W3105284836","https://openalex.org/W3146279708","https://openalex.org/W4235968347","https://openalex.org/W4240163901","https://openalex.org/W4243519499","https://openalex.org/W4243585432","https://openalex.org/W4254672563"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2155174752","https://openalex.org/W2991771859","https://openalex.org/W2619968078","https://openalex.org/W4324145463","https://openalex.org/W1593362825","https://openalex.org/W2158157809","https://openalex.org/W2136656113","https://openalex.org/W321873635","https://openalex.org/W1489784118"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"PIMA-Logic,":[5],"as":[6,94,145],"a":[7,28,95,99,146],"novel":[8],"<u>P</u>rocessing-<u>i</u>n-<u>M</u>emory":[9],"<u>A</u>rchitecture":[10],"for":[11],"highly":[12],"flexible":[13],"and":[14,69,89,98,115,123,155,163],"efficient":[15],"<u>Logic</u>":[16],"computation.":[17],"Insteadof":[18],"integrating":[19],"complex":[20,58],"logic":[21,34,59,127],"units":[22],"in":[23,40],"cost-sensitive":[24],"memory,":[25],"PIMA-Logic":[26,109,144],"exploits":[27],"hardware-friendly":[29],"approach":[30],"to":[31,64,113,120,130,161],"implement":[32,136],"Boolean":[33],"functions":[35,60],"between":[36,61],"operands":[37,63],"either":[38],"located":[39],"the":[41,45,67],"same":[42,46],"row":[43],"or":[44],"column":[47],"within":[48],"entire":[49],"memory":[50,97],"arrays.":[51],"Furthermore,":[52],"it":[53,90,152],"can":[54,91,110],"efficiently":[55],"process":[56],"more":[57],"multiple":[62],"further":[65,135],"reduce":[66],"latency":[68],"power-hungry":[70],"data":[71,139],"movement.":[72],"The":[73,103],"proposed":[74],"architecture":[75],"is":[76],"developed":[77],"based":[78,142],"on":[79,125,143],"Spin":[80],"Orbit":[81],"Torque":[82],"Magnetic":[83],"Random":[84],"Access":[85],"Memory":[86],"(SOT-MRAM)":[87],"array":[88],"simultaneously":[92],"work":[93],"non-volatile":[96],"reconfigurable":[100],"in-memory":[101,138],"logic.":[102],"device-to-architecture":[104],"co-simulation":[105],"results":[106],"show":[107],"that":[108],"achieve":[111],"up":[112],"56%":[114],"31.6%":[116],"improvements":[117],"with":[118],"respect":[119],"overall":[121],"energy":[122,158],"delay":[124],"combinational":[126],"benchmarks":[128],"compared":[129,160],"recent":[131,164],"Pinatubo":[132],"architecture.":[133],"We":[134],"an":[137],"encryption":[140],"engine":[141],"case":[147],"study.":[148],"With":[149],"AES":[150],"application,":[151],"shows":[153],"77.2%":[154],"21%":[156],"lower":[157],"consumption":[159],"CMOS-ASIC":[162],"RIMPA":[165],"implementation,":[166],"respectively.":[167]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":7}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2018-06-29T00:00:00"}