{"id":"https://openalex.org/W2809300180","doi":"https://doi.org/10.1145/3195970.3196054","title":"Formal micro-architectural analysis of on-chip ring networks","display_name":"Formal micro-architectural analysis of on-chip ring networks","publication_year":2018,"publication_date":"2018-06-19","ids":{"openalex":"https://openalex.org/W2809300180","doi":"https://doi.org/10.1145/3195970.3196054","mag":"2809300180"},"language":"en","primary_location":{"id":"doi:10.1145/3195970.3196054","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3196054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002660269","display_name":"Perry van Wesel","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Perry van Wesel","raw_affiliation_strings":["Eindhoven University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088595514","display_name":"Julien Schmaltz","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Julien Schmaltz","raw_affiliation_strings":["Eindhoven University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I83019370"],"apc_list":null,"apc_paid":null,"fwci":0.2262,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.36127449,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8408503532409668},{"id":"https://openalex.org/keywords/liveness","display_name":"Liveness","score":0.7921565175056458},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7916260957717896},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.6952816843986511},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6645766496658325},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5040201544761658},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.48162907361984253},{"id":"https://openalex.org/keywords/ring","display_name":"Ring (chemistry)","score":0.4607563614845276},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4581356346607208},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4260760247707367},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4240453243255615},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32880741357803345},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.21647092700004578}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8408503532409668},{"id":"https://openalex.org/C15569618","wikidata":"https://www.wikidata.org/wiki/Q3561421","display_name":"Liveness","level":2,"score":0.7921565175056458},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7916260957717896},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.6952816843986511},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6645766496658325},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5040201544761658},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.48162907361984253},{"id":"https://openalex.org/C2780378348","wikidata":"https://www.wikidata.org/wiki/Q25351438","display_name":"Ring (chemistry)","level":2,"score":0.4607563614845276},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4581356346607208},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4260760247707367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4240453243255615},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32880741357803345},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.21647092700004578},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/3195970.3196054","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3195970.3196054","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/9477eeee-b001-4ae1-bd15-609b9e0f9b71","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/9477eeee-b001-4ae1-bd15-609b9e0f9b71","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"van Wesel, P & Schmaltz, J 2018, Formal micro-architectural analysis of on-chip ring networks. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018., 94, ACM/IEEE, New York, 55th Annual Design Automation Conference, (DAC2018), San Francisco, California, United States, 24/06/18. https://doi.org/10.1145/3195970.3196054","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:tue:oai:pure.tue.nl:publications/9477eeee-b001-4ae1-bd15-609b9e0f9b71","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/9477eeee-b001-4ae1-bd15-609b9e0f9b71","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the 55th Annual Design Automation Conference, DAC 2018","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1575212675","https://openalex.org/W1585721824","https://openalex.org/W1988635830","https://openalex.org/W1995387037","https://openalex.org/W2024390509","https://openalex.org/W2034592364","https://openalex.org/W2046430349","https://openalex.org/W2092665266","https://openalex.org/W2130183852","https://openalex.org/W2163975534","https://openalex.org/W2187915755","https://openalex.org/W2522679276","https://openalex.org/W3148242158","https://openalex.org/W4245160202"],"related_works":["https://openalex.org/W1867637656","https://openalex.org/W112055548","https://openalex.org/W2329232208","https://openalex.org/W3161493205","https://openalex.org/W1976012348","https://openalex.org/W4297990507","https://openalex.org/W2144357574","https://openalex.org/W4230458348","https://openalex.org/W1966325333","https://openalex.org/W3198758847"],"abstract_inverted_index":{"In":[0],"the":[1,7,19,25,57,66,97,115],"realm":[2],"of":[3,24,40,71,99],"Multi-Processors":[4],"System-on-Chip":[5],"(MPSoC's),":[6],"Network-on-Chip":[8],"(NoC)":[9],"connecting":[10],"all":[11],"system":[12],"components":[13],"plays":[14],"a":[15,84,103,109],"crucial":[16],"role":[17],"in":[18,45,114],"overall":[20],"correctness":[21],"and":[22,38,69,96],"performance":[23],"system.":[26],"Recent":[27],"papers":[28],"have":[29],"proposed":[30],"several":[31],"ring":[32,73,88],"based":[33],"NoC":[34],"solutions.":[35],"The":[36,106],"description":[37],"analysis":[39,70,107],"these":[41],"micro-architectures":[42],"are":[43],"informal":[44],"nature.":[46],"Text":[47],"is":[48],"used":[49],"to":[50,86],"argue":[51],"about,":[52],"e.g.,":[53],"deadlock":[54,93,111],"freedom.":[55],"For":[56],"first":[58],"time,":[59],"this":[60],"paper":[61],"proposes":[62],"an":[63,76],"environment":[64],"for":[65],"formal":[67],"modelling":[68],"such":[72],"architectures":[74],"with":[75],"emphasis":[77],"on":[78,102],"liveness":[79],"properties.":[80],"Our":[81],"contribution":[82],"includes":[83],"language":[85],"model":[87],"micro-architectures,":[89],"invariant":[90],"generation":[91],"techniques,":[92],"freedom":[94],"verification,":[95],"application":[98],"our":[100],"approach":[101],"realistic":[104],"case-study.":[105],"reveals":[108],"possible":[110],"not":[112],"mentioned":[113],"original":[116],"paper.":[117]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
