{"id":"https://openalex.org/W2805756159","doi":"https://doi.org/10.1145/3194554.3194613","title":"Gate-Controlled Memristors and their Applications in Neuromorphic Architectures","display_name":"Gate-Controlled Memristors and their Applications in Neuromorphic Architectures","publication_year":2018,"publication_date":"2018-05-30","ids":{"openalex":"https://openalex.org/W2805756159","doi":"https://doi.org/10.1145/3194554.3194613","mag":"2805756159"},"language":"en","primary_location":{"id":"doi:10.1145/3194554.3194613","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194613","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194613","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194613","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102854294","display_name":"Eric Herrmann","orcid":"https://orcid.org/0000-0003-3615-9331"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eric Herrmann","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH, USA"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046869634","display_name":"Rashmi Jha","orcid":"https://orcid.org/0000-0002-2656-5945"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rashmi Jha","raw_affiliation_strings":["University of Cincinnati, Cincinnati, OH, USA"],"affiliations":[{"raw_affiliation_string":"University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5102854294"],"corresponding_institution_ids":["https://openalex.org/I63135867"],"apc_list":null,"apc_paid":null,"fwci":0.1309,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.47140204,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"385","last_page":"390"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9527078866958618},{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.9091180562973022},{"id":"https://openalex.org/keywords/mnist-database","display_name":"MNIST database","score":0.9087976217269897},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.7592672109603882},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6598944067955017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5581480264663696},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.5426985621452332},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5189497470855713},{"id":"https://openalex.org/keywords/analog-computer","display_name":"Analog computer","score":0.444872111082077},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4435434639453888},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3670952320098877},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.36534079909324646},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29041239619255066},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26530587673187256},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.2153734564781189},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17713496088981628}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9527078866958618},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.9091180562973022},{"id":"https://openalex.org/C190502265","wikidata":"https://www.wikidata.org/wiki/Q17069496","display_name":"MNIST database","level":3,"score":0.9087976217269897},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.7592672109603882},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6598944067955017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5581480264663696},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.5426985621452332},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5189497470855713},{"id":"https://openalex.org/C90915687","wikidata":"https://www.wikidata.org/wiki/Q63759","display_name":"Analog computer","level":2,"score":0.444872111082077},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4435434639453888},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3670952320098877},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.36534079909324646},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29041239619255066},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26530587673187256},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.2153734564781189},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17713496088981628},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3194554.3194613","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194613","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194613","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3194554.3194613","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194613","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194613","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"sustainable_development_goals":[{"display_name":"Quality Education","score":0.5899999737739563,"id":"https://metadata.un.org/sdg/4"}],"awards":[{"id":"https://openalex.org/G2384248369","display_name":null,"funder_award_id":"ECCS 1556294","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5171267899","display_name":"CAREER:Novel Nanoelectronic Reconfigurable Synaptic Memory Devices","funder_award_id":"1556294","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5568057531","display_name":null,"funder_award_id":"1556294","funder_id":"https://openalex.org/F4320337392","funder_display_name":"Division of Electrical, Communications and Cyber Systems"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2805756159.pdf","grobid_xml":"https://content.openalex.org/works/W2805756159.grobid-xml"},"referenced_works_count":3,"referenced_works":["https://openalex.org/W2279573005","https://openalex.org/W2307193480","https://openalex.org/W2791627263"],"related_works":["https://openalex.org/W3137378424","https://openalex.org/W2809732489","https://openalex.org/W4292697011","https://openalex.org/W4287780255","https://openalex.org/W3023361272","https://openalex.org/W2909534142","https://openalex.org/W3212508523","https://openalex.org/W3207218810","https://openalex.org/W1995352804","https://openalex.org/W1872623660"],"abstract_inverted_index":{"We":[0],"discuss":[1],"the":[2,32,37,46,85,94],"theory":[3],"of":[4,15,22,31,48],"gated":[5,97],"memristive":[6],"devices,":[7],"which":[8],"exhibit":[9],"continuous":[10],"states":[11],"over":[12],"three":[13],"orders":[14],"magnitude":[16],"and":[17,35,67],"can":[18,99],"be":[19],"programmed":[20],"independently":[21],"reading.":[23],"A":[24],"model":[25],"is":[26,61,77,91],"generated":[27],"by":[28],"using":[29],"knowledge":[30],"device":[33],"physics":[34],"fitting":[36],"parameters":[38],"to":[39,79,92,101],"measured":[40],"data.":[41],"The":[42,71,89],"gate-controlled":[43],"memristor":[44],"simplifies":[45],"implementation":[47],"analog":[49,73,102],"artificial":[50],"neural":[51,74,75,103],"network":[52,76],"architectures":[53],"significantly.":[54],"Using":[55],"this,":[56],"a":[57,65],"very":[58],"simple":[59],"architecture":[60],"presented,":[62],"along":[63],"with":[64],"simulation":[66],"its":[68],"performance":[69],"metrics.":[70],"simulated":[72],"able":[78],"achieve":[80],"88.9":[81],"percent":[82],"accuracy":[83],"on":[84],"MNIST":[86],"test":[87],"set.":[88],"objective":[90],"demonstrate":[93],"advantages":[95],"that":[96],"memristors":[98],"give":[100],"networks.":[104]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
