{"id":"https://openalex.org/W2805929676","doi":"https://doi.org/10.1145/3194554.3194579","title":"A Comparative Study of Local Net Modeling Using Machine Learning","display_name":"A Comparative Study of Local Net Modeling Using Machine Learning","publication_year":2018,"publication_date":"2018-05-30","ids":{"openalex":"https://openalex.org/W2805929676","doi":"https://doi.org/10.1145/3194554.3194579","mag":"2805929676"},"language":"en","primary_location":{"id":"doi:10.1145/3194554.3194579","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194579","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194579","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194579","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008041651","display_name":"Jackson Melchert","orcid":"https://orcid.org/0000-0002-8232-1603"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jackson Melchert","raw_affiliation_strings":["University of Wisconsin - Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin - Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100714037","display_name":"Boyu Zhang","orcid":"https://orcid.org/0000-0002-7027-4942"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Boyu Zhang","raw_affiliation_strings":["University of Wisconsin - Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin - Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072204999","display_name":"Azadeh Davoodi","orcid":"https://orcid.org/0000-0001-5213-2556"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Azadeh Davoodi","raw_affiliation_strings":["University of Wisconsin - Madison, Madison, WI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin - Madison, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"273","last_page":"278"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7911607027053833},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6676709651947021},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5309911370277405},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.5074638724327087},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.48472118377685547},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.43593576550483704},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0880109965801239},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08649459481239319}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7911607027053833},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6676709651947021},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5309911370277405},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.5074638724327087},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.48472118377685547},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.43593576550483704},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0880109965801239},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08649459481239319},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3194554.3194579","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194579","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194579","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3194554.3194579","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3194554.3194579","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/3194554.3194579","source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1063008855","display_name":"SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits","funder_award_id":"1608040","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2805929676.pdf","grobid_xml":"https://content.openalex.org/works/W2805929676.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W1630964756","https://openalex.org/W1976496997","https://openalex.org/W1999116995","https://openalex.org/W2023532618","https://openalex.org/W2085310683","https://openalex.org/W2125831674","https://openalex.org/W2161629461","https://openalex.org/W2293811830","https://openalex.org/W2604486584","https://openalex.org/W2604690070","https://openalex.org/W2605557116"],"related_works":["https://openalex.org/W2961085424","https://openalex.org/W4306674287","https://openalex.org/W3046775127","https://openalex.org/W3107602296","https://openalex.org/W4394896187","https://openalex.org/W3170094116","https://openalex.org/W4386462264","https://openalex.org/W4364306694","https://openalex.org/W4312192474","https://openalex.org/W4283697347"],"abstract_inverted_index":{"Local":[0],"nets":[1,23,35,160],"are":[2,36,162],"by":[3,70],"default":[4],"ignored":[5],"during":[6],"global":[7,49,75,168],"routing":[8,95],"but":[9],"can":[10],"contribute":[11],"to":[12,17,137],"a":[13,81,98],"high":[14],"percentage":[15],"(up":[16],"30%)":[18],"of":[19,22,158],"total":[20],"number":[21],"in":[24,164],"the":[25,93,103,127,156],"design.":[26],"Prior":[27],"work":[28,57,139],"proposed":[29],"simple":[30],"models":[31],"for":[32,155],"how":[33],"local":[34,60,71,88,159],"routed":[37,163],"and":[38,51,84,116,131,146],"showed":[39],"benefits":[40],"such":[41],"as":[42,80,85],"better":[43,52,154],"congestion":[44],"analysis":[45],"post-placement,":[46],"integration":[47],"with":[48],"routing,":[50],"track":[53],"assignment.":[54],"In":[55],"this":[56,79],"we":[58,105,114],"study":[59,115],"net":[61],"modeling":[62],"using":[63,97],"machine":[64,108],"learning.":[65],"Our":[66,150],"model":[67,78,134,151],"predicts":[68],"utilization":[69,90],"routes":[72],"inside":[73],"each":[74],"cell.":[76,169],"We":[77,125],"regression":[82],"problem":[83,104],"reference":[86],"use":[87],"route":[89],"data":[91],"from":[92],"detailed":[94],"stage":[96],"commercial":[99],"tool.":[100],"To":[101],"solve":[102],"identify":[106,126],"suitable":[107],"learning":[109],"algorithms.":[110],"Within":[111],"our":[112,133],"modeling,":[113],"rank":[117],"different":[118],"features":[119,130],"which":[120,140,161],"utilize":[121],"various":[122],"layout":[123],"attributes.":[124],"most":[128],"beneficial":[129],"show":[132],"performs":[135,153],"superior":[136],"prior":[138],"were":[141],"based":[142],"on":[143],"pin":[144],"density":[145],"Steiner":[147],"tree":[148],"models.":[149],"also":[152],"subset":[157],"more":[165],"than":[166],"one":[167]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}