{"id":"https://openalex.org/W2807112875","doi":"https://doi.org/10.1145/3194554.3194567","title":"Electromigration Design Rule aware Global and Detailed Routing Algorithm","display_name":"Electromigration Design Rule aware Global and Detailed Routing Algorithm","publication_year":2018,"publication_date":"2018-05-30","ids":{"openalex":"https://openalex.org/W2807112875","doi":"https://doi.org/10.1145/3194554.3194567","mag":"2807112875"},"language":"en","primary_location":{"id":"doi:10.1145/3194554.3194567","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3194554.3194567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101916099","display_name":"Xiaotao Jia","orcid":"https://orcid.org/0000-0003-2207-6092"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaotao Jia","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100625942","display_name":"Jing Wang","orcid":"https://orcid.org/0000-0001-8628-8452"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jing Wang","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111983610","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101929509","display_name":"Qiang Zhou","orcid":"https://orcid.org/0000-0003-1348-8861"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Zhou","raw_affiliation_strings":["Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101916099"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.05958834,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"16","issue":null,"first_page":"267","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9763000011444092,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electromigration","display_name":"Electromigration","score":0.9176647067070007},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.7232019901275635},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6735597848892212},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6657658815383911},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.48960763216018677},{"id":"https://openalex.org/keywords/multipath-routing","display_name":"Multipath routing","score":0.48503822088241577},{"id":"https://openalex.org/keywords/metrics","display_name":"Metrics","score":0.4797186255455017},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4676715135574341},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43455246090888977},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42870959639549255},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.42764461040496826},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.4235309064388275},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3558822274208069},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3355662226676941},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.2984932065010071},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.21453627943992615},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19001144170761108},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16387060284614563},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.162186861038208},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14745542407035828},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13469764590263367},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10565000772476196}],"concepts":[{"id":"https://openalex.org/C138055206","wikidata":"https://www.wikidata.org/wiki/Q1319010","display_name":"Electromigration","level":2,"score":0.9176647067070007},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7232019901275635},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6735597848892212},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6657658815383911},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.48960763216018677},{"id":"https://openalex.org/C76522221","wikidata":"https://www.wikidata.org/wiki/Q5035396","display_name":"Multipath routing","level":5,"score":0.48503822088241577},{"id":"https://openalex.org/C195780805","wikidata":"https://www.wikidata.org/wiki/Q1535986","display_name":"Metrics","level":5,"score":0.4797186255455017},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4676715135574341},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43455246090888977},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42870959639549255},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.42764461040496826},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.4235309064388275},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3558822274208069},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3355662226676941},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.2984932065010071},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.21453627943992615},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19001144170761108},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16387060284614563},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.162186861038208},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14745542407035828},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13469764590263367},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10565000772476196},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3194554.3194567","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3194554.3194567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1978465272","https://openalex.org/W1982222146","https://openalex.org/W2007719944","https://openalex.org/W2008074787","https://openalex.org/W2033675353","https://openalex.org/W2071520186","https://openalex.org/W2083090974","https://openalex.org/W2150608324","https://openalex.org/W2516941205","https://openalex.org/W2605578718","https://openalex.org/W3147058567","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2004615523","https://openalex.org/W2055638565","https://openalex.org/W2138118262","https://openalex.org/W2542708587","https://openalex.org/W4229007131","https://openalex.org/W2364197307","https://openalex.org/W4229489461","https://openalex.org/W2099825670","https://openalex.org/W1965160169","https://openalex.org/W2380223518"],"abstract_inverted_index":{"Electromigration":[0,15],"(EM)":[1],"in":[2,45],"interconnects":[3],"is":[4,61,76,83],"becoming":[5],"a":[6],"major":[7],"concern":[8],"as":[9,63],"the":[10,31,100],"scaling":[11],"of":[12,33,109,117],"technology":[13],"nodes.":[14],"affects":[16],"chip":[17],"performance":[18],"and":[19,28,48,57,120],"signal":[20,110],"integrity":[21],"seriously":[22],"by":[23,112],"generating":[24],"shorts":[25],"or":[26],"opens,":[27],"then":[29,84],"shortens":[30],"life-time":[32],"integrated":[34],"circuits.":[35],"In":[36,67],"this":[37],"paper,":[38],"we":[39],"propose":[40],"an":[41,71],"EM-aware":[42,73,80,102],"routing":[43,50,69,98],"algorithm":[44,75,103],"both":[46],"global":[47,68],"detailed":[49,81],"stages.":[51],"Based":[52],"on":[53,87],"physics-based":[54],"EM":[55,59,107],"modeling":[56],"analysis,":[58],"issue":[60],"modeled":[62],"physical":[64],"design":[65],"rule.":[66],"stage,":[70],"efficient":[72],"Mazerouting":[74],"implemented.":[77],"An":[78],"concurrent":[79],"router":[82],"proposed":[85,101],"based":[86],"multi-commodity":[88],"flow":[89],"method.":[90],"Experimental":[91],"results":[92],"show":[93],"that":[94],"comparing":[95],"with":[96,114],"general":[97],"algorithm,":[99],"could":[104],"effectively":[105],"reduce":[106],"risk":[108],"wires":[111],"92%":[113],"slight":[115],"increasing":[116],"wire":[118],"length":[119],"via":[121],"count.":[122]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
