{"id":"https://openalex.org/W2806741041","doi":"https://doi.org/10.1145/3194554.3194556","title":"Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration","display_name":"Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration","publication_year":2018,"publication_date":"2018-05-30","ids":{"openalex":"https://openalex.org/W2806741041","doi":"https://doi.org/10.1145/3194554.3194556","mag":"2806741041"},"language":"en","primary_location":{"id":"doi:10.1145/3194554.3194556","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3194554.3194556","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090740843","display_name":"Peishan Tu","orcid":"https://orcid.org/0000-0002-1727-8119"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Peishan Tu","raw_affiliation_strings":["The Chinese University of Hong Kong, HongKong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, HongKong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080499552","display_name":"Chak-Wa Pui","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chak-Wa Pui","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline F.Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090740843"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05100392,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"261","last_page":"266"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7279201149940491},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6691378951072693},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.6647928357124329},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6484250426292419},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.47187677025794983},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.46091440320014954},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4044056832790375},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20088785886764526},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18501761555671692},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09459680318832397}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7279201149940491},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6691378951072693},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.6647928357124329},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6484250426292419},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.47187677025794983},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.46091440320014954},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4044056832790375},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20088785886764526},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18501761555671692},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09459680318832397},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3194554.3194556","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3194554.3194556","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W273955616","https://openalex.org/W1987877061","https://openalex.org/W2016999260","https://openalex.org/W2032264883","https://openalex.org/W2041176678","https://openalex.org/W2046079692","https://openalex.org/W2049111024","https://openalex.org/W2053902150","https://openalex.org/W2060002782","https://openalex.org/W2064529033","https://openalex.org/W2124501077","https://openalex.org/W2125831674","https://openalex.org/W2133527739","https://openalex.org/W2137432232","https://openalex.org/W2149603028","https://openalex.org/W2151278468","https://openalex.org/W2248975694","https://openalex.org/W2772001064","https://openalex.org/W2916090591"],"related_works":["https://openalex.org/W2075067217","https://openalex.org/W4254709952","https://openalex.org/W2026034687","https://openalex.org/W1687060458","https://openalex.org/W1976154696","https://openalex.org/W2353466952","https://openalex.org/W2609535666","https://openalex.org/W4240977383","https://openalex.org/W4256116802","https://openalex.org/W4235738893"],"abstract_inverted_index":{"In":[0,28],"global":[1,43,66],"routing,":[2],"both":[3],"timing":[4,76,113],"and":[5,68,77,94,121],"routability":[6,78,120],"are":[7],"critical":[8],"criterions":[9],"to":[10,37,45,73,86,97],"measure":[11],"the":[12,50,62,99],"performance":[13],"of":[14,60],"a":[15,31,53,65,92],"design.":[16],"However,":[17],"these":[18],"two":[19],"objectives":[20],"naturally":[21],"conflict":[22],"with":[23,115],"each":[24],"other":[25],"during":[26],"routing.":[27],"this":[29],"paper,":[30],"tree":[32,40],"surgery":[33],"technique":[34],"is":[35],"presented":[36],"adjust":[38],"routing":[39,44,58],"topologies":[41,59],"in":[42,119,133],"fix":[46],"timing.":[47],"We":[48,80],"formulate":[49],"problem":[51],"as":[52],"quadratic":[54],"program(QP),":[55],"which":[56,90],"adjusts":[57],"all":[61],"nets":[63],"from":[64],"perspective":[67],"takes":[69],"congestion":[70],"into":[71],"consideration":[72],"trade":[74],"off":[75],"objectives.":[79],"also":[81],"apply":[82],"machine":[83,124],"learning-based":[84,125],"techniques":[85],"accelerate":[87],"our":[88,108,128],"algorithm,":[89],"offers":[91],"fast":[93],"effective":[95],"way":[96],"solve":[98],"problem.":[100],"Experimental":[101],"results":[102,129],"on":[103],"ICCAD~2015":[104],"benchmarks":[105],"show":[106],"that":[107],"algorithms":[109],"can":[110,130],"achieve":[111],"10.12%":[112],"improvement":[114],"no":[116],"significant":[117],"degradation":[118],"wirelength.":[122],"With":[123],"acceleration":[126],"(MLA),":[127],"be":[131],"obtained":[132],"almost":[134],"negligible":[135],"runtime.":[136]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
