{"id":"https://openalex.org/W2804329950","doi":"https://doi.org/10.1145/3185089.3185136","title":"A Study of Data Layout in Multi-channel Processing-In-Memory Architecture","display_name":"A Study of Data Layout in Multi-channel Processing-In-Memory Architecture","publication_year":2018,"publication_date":"2018-02-08","ids":{"openalex":"https://openalex.org/W2804329950","doi":"https://doi.org/10.1145/3185089.3185136","mag":"2804329950"},"language":"en","primary_location":{"id":"doi:10.1145/3185089.3185136","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3185089.3185136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 7th International Conference on Software and Computer Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046912551","display_name":"Taeyang Jeong","orcid":"https://orcid.org/0000-0001-9110-6502"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taeyang Jeong","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068657822","display_name":"\ucd5c\ub450\ud5cc","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Duheon Choi","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048986257","display_name":"Sangwoo Han","orcid":"https://orcid.org/0000-0003-0741-1075"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sangwoo Han","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084016800","display_name":"Eui-Young Chung","orcid":"https://orcid.org/0000-0003-2013-8763"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Eui-Young Chung","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4751,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61709737,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"134","last_page":"138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8442050814628601},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6079573631286621},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5937197208404541},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5344561338424683},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.48969605565071106},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.47658488154411316},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4701032042503357},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4682876467704773},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.4593397378921509},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.45924121141433716},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4480232000350952},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4420027434825897},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.43899962306022644},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.43503010272979736},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4168010652065277},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.4158194065093994},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.41548702120780945},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.41115936636924744},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4002547860145569},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33699727058410645}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8442050814628601},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6079573631286621},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5937197208404541},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5344561338424683},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.48969605565071106},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.47658488154411316},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4701032042503357},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4682876467704773},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.4593397378921509},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.45924121141433716},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4480232000350952},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4420027434825897},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.43899962306022644},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.43503010272979736},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4168010652065277},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.4158194065093994},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.41548702120780945},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.41115936636924744},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4002547860145569},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33699727058410645},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3185089.3185136","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3185089.3185136","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 7th International Conference on Software and Computer Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1981943579","https://openalex.org/W1983096721","https://openalex.org/W2078141470","https://openalex.org/W2093524602","https://openalex.org/W2112547256","https://openalex.org/W2112980698","https://openalex.org/W2114440330","https://openalex.org/W2141443190","https://openalex.org/W2518511512","https://openalex.org/W3125984961","https://openalex.org/W4239722617","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W3180803030","https://openalex.org/W4225739994","https://openalex.org/W4321062910","https://openalex.org/W2753615087","https://openalex.org/W4297924271","https://openalex.org/W2168550483","https://openalex.org/W2993507867","https://openalex.org/W2768900401","https://openalex.org/W3025845664","https://openalex.org/W3213903995"],"abstract_inverted_index":{"In":[0,86],"modern":[1],"computing":[2,24,98],"hardware,":[3],"the":[4,14,28],"performance":[5,21],"gap":[6],"between":[7],"processor":[8],"and":[9,32],"memory":[10,35,69,84],"is":[11,39,55,66,89,94,113],"one":[12],"of":[13,23,30],"most":[15],"significant":[16],"factors":[17],"that":[18,56,93],"limits":[19],"overall":[20],"improvement":[22],"system.":[25,85,99],"Also,":[26],"with":[27,96],"advent":[29],"multicore":[31],"manycore":[33],"system,":[34],"bandwidth":[36],"per":[37],"core":[38],"decreasing":[40],"constantly.":[41],"To":[42],"solve":[43],"this":[44],"problem,":[45],"recently,":[46],"many":[47],"researchers":[48],"are":[49,59],"interested":[50],"in":[51],"Processing-In-Memory":[52],"(PIM).":[53],"PIM":[54,88],"processing":[57],"elements":[58],"attached":[60],"to":[61,116],"memory-side,":[62],"so":[63],"near-memory-processing":[64],"which":[65],"suitable":[67],"for":[68,108],"intensive":[70],"application":[71],"can":[72],"be":[73,117],"possible.":[74],"Various":[75],"researches":[76],"studied":[77],"PIM,":[78],"but":[79],"it":[80],"was":[81],"just":[82],"single-channel":[83],"addition,":[87],"a":[90],"new":[91],"architecture":[92],"different":[95],"conventional":[97],"Thus,":[100],"common":[101],"data":[102,111],"layout":[103,112],"cannot":[104],"become":[105],"optimal":[106],"case":[107],"PIM.":[109],"Optimal":[110],"also":[114],"needed":[115],"studied.":[118]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}