{"id":"https://openalex.org/W2803860543","doi":"https://doi.org/10.1145/3185089.3185134","title":"CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA","display_name":"CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA","publication_year":2018,"publication_date":"2018-02-08","ids":{"openalex":"https://openalex.org/W2803860543","doi":"https://doi.org/10.1145/3185089.3185134","mag":"2803860543"},"language":"en","primary_location":{"id":"doi:10.1145/3185089.3185134","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3185089.3185134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 7th International Conference on Software and Computer Applications","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054291013","display_name":"Jeongbin Kim","orcid":"https://orcid.org/0000-0002-5950-0056"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Jeongbin Kim","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100685794","display_name":"Ki Tae Kim","orcid":"https://orcid.org/0000-0002-5692-1189"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Ki Tae Kim","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084016800","display_name":"Eui-Young Chung","orcid":"https://orcid.org/0000-0003-2013-8763"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Eui-Young Chung","raw_affiliation_strings":["Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Electronic Eng., Yonsei University, Seoul, Republic of Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5054291013"],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46166312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"312","last_page":"316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9129237532615662},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.874352216720581},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6601207852363586},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4780590832233429},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4154316782951355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4043923616409302},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.385246604681015},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3489070534706116},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3389834761619568},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11377841234207153}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9129237532615662},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.874352216720581},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6601207852363586},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4780590832233429},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4154316782951355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4043923616409302},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.385246604681015},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3489070534706116},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3389834761619568},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11377841234207153},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3185089.3185134","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3185089.3185134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 7th International Conference on Software and Computer Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1964643833","https://openalex.org/W2031539925","https://openalex.org/W2091685042","https://openalex.org/W2138383740","https://openalex.org/W2139637699","https://openalex.org/W2168493238","https://openalex.org/W2342889976","https://openalex.org/W2562517775","https://openalex.org/W2591922920"],"related_works":["https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2117956479","https://openalex.org/W2053477566"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Array":[3],"(FPGA)":[4],"is":[5,11],"a":[6,28,36,57,63,80,134],"reconfigurable":[7],"circuit":[8,30,38],"and":[9,23,83,132,167],"it":[10,47,84],"used":[12,41],"for":[13,79,120],"various":[14],"applications":[15],"such":[16],"as":[17,35,56],"image":[18],"processing,":[19],"digital":[20],"signal":[21],"processing":[22],"neural":[24],"network.":[25],"FPGA":[26,101,107,113,124,139,144],"adopts":[27,54],"logic":[29],"called":[31],"Look-Up":[32],"Table":[33],"(LUT)":[34],"basic":[37],"structure.":[39],"Commonly":[40],"FPGAs":[42,61,82],"have":[43,62],"volatile":[44],"characteristic":[45,128],"because":[46],"consists":[48],"of":[49,67,129,153,156],"SRAM":[50,55],"based":[51,100,123,145],"LUT":[52,75,99,122,148,182],"that":[53,88,162],"memory":[58],"cell.":[59],"Volatile":[60],"disadvantage":[64],"in":[65,92],"terms":[66],"power":[68,163],"management":[69],"efficiency.":[70],"Variation-Tolerant":[71],"Non-Volatile":[72],"STT-MRAM":[73],"(VTNV)":[74],"has":[76,85],"been":[77],"studied":[78],"non-volatile":[81,135,143],"unique":[86,127],"characteristics":[87],"can":[89],"only":[90],"operate":[91,103,150],"the":[93],"half":[94],"clock":[95],"period.":[96],"Accordingly,":[97],"VTNV":[98,121,130,147,157,181],"cannot":[102],"normally":[104],"with":[105,125],"conventional":[106],"CAD":[108,114,140],"tool":[109,118,141],"flow.":[110],"We":[111],"propose":[112],"(Computer":[115],"Aided":[116],"Design)":[117],"flow":[119],"supporting":[126],"LUT,":[131,158],"implement":[133],"FPGA.":[136],"Through":[137],"proposed":[138],"flow,":[142],"on":[146],"could":[149],"normally.":[151],"Because":[152],"high":[154],"parameters":[155],"experimental":[159],"results":[160],"show":[161],"increases":[164,171],"by":[165,172,179],"29%":[166],"critical":[168],"path":[169],"delay":[170],"16%,":[173],"but":[174],"it'll":[175],"be":[176],"improved":[177],"sufficiently":[178],"future":[180],"researches.":[183]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}