{"id":"https://openalex.org/W2791191785","doi":"https://doi.org/10.1145/3177540.3178244","title":"Compact-2D","display_name":"Compact-2D","publication_year":2018,"publication_date":"2018-03-16","ids":{"openalex":"https://openalex.org/W2791191785","doi":"https://doi.org/10.1145/3177540.3178244","mag":"2791191785"},"language":"en","primary_location":{"id":"doi:10.1145/3177540.3178244","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3178244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041659450","display_name":"Bon Woong Ku","orcid":"https://orcid.org/0000-0001-9770-0297"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bon Woong Ku","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088565714","display_name":"Kyungwook Chang","orcid":"https://orcid.org/0000-0002-8513-9890"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kyungwook Chang","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":11.6893,"has_fulltext":false,"cited_by_count":58,"citation_normalized_percentile":{"value":0.99351088,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"97"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.983299970626831,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6292612552642822},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.556654691696167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5554302930831909},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5397322177886963},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.5291398167610168},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5182230472564697},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4949299693107605},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.470119833946228},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44302308559417725},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4125114381313324},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33768948912620544},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3077126145362854},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2750226855278015},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.25574791431427},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.17346233129501343},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15202656388282776}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6292612552642822},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.556654691696167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5554302930831909},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5397322177886963},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.5291398167610168},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5182230472564697},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4949299693107605},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.470119833946228},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44302308559417725},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4125114381313324},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33768948912620544},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3077126145362854},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2750226855278015},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25574791431427},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.17346233129501343},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15202656388282776},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3177540.3178244","is_oa":false,"landing_page_url":"https://doi.org/10.1145/3177540.3178244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2018 International Symposium on Physical Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2002806561","https://openalex.org/W2018540545","https://openalex.org/W2027384865","https://openalex.org/W2141361504","https://openalex.org/W2317953216","https://openalex.org/W2484447298","https://openalex.org/W2509008645","https://openalex.org/W2538167498","https://openalex.org/W2538575430","https://openalex.org/W2582668146"],"related_works":["https://openalex.org/W2051886008","https://openalex.org/W2151657833","https://openalex.org/W2035081722","https://openalex.org/W2070693700","https://openalex.org/W1488283129","https://openalex.org/W3172718840","https://openalex.org/W2365114398","https://openalex.org/W1617216077","https://openalex.org/W2156138647","https://openalex.org/W1987597317"],"abstract_inverted_index":{"The":[0,40],"recent":[1],"advancement":[2],"of":[3,48,56,65,155],"wafer":[4],"bonding":[5],"technology":[6],"offers":[7,121,170],"fine-grained":[8],"and":[9,34,51,85,109,176],"silicon-space":[10],"overhead-free":[11],"3D":[12,18,38,63,137],"interconnections":[13],"in":[14,130,143],"face-to-face":[15],"(F2F)":[16],"bonded":[17],"ICs.":[19,39],"In":[20,118],"this":[21],"paper,":[22],"we":[23,146],"propose":[24],"a":[25,54,66,101,148],"full-chip":[26],"RTL-to-GDSII":[27],"physical":[28],"design":[29,116],"solution":[30],"to":[31,58,113,127,150,172],"build":[32],"high-density":[33],"commercial-quality":[35],"two-tier":[36,67],"F2F-bonded":[37],"state-of-the-art":[41],"flow":[42,88],"named":[43,89],"Shrunk-2D":[44],"(S2D)":[45],"requires":[46],"shrinking":[47],"standard":[49],"cells":[50],"interconnects":[52],"by":[53,135],"factor":[55],"50%":[57],"fit":[59],"into":[60],"the":[61,111,114,152],"target":[62],"footprint":[64],"design.":[68],"This,":[69],"unfortunately,":[70],"necessitates":[71],"commercial":[72,182],"place/route":[73],"engines":[74],"that":[75,124,166],"handle":[76],"one":[77],"node":[78],"smaller":[79],"geometries,":[80],"which":[81,139],"can":[82],"be":[83,128],"challenging":[84],"costly.":[86],"Our":[87,162],"Compact-2D":[90],"(C2D)":[91],"does":[92],"not":[93],"require":[94],"any":[95,186],"geometry":[96],"shrinking.":[97],"Instead,":[98],"C2D":[99,120,169],"implements":[100],"2D":[102,183],"IC":[103],"with":[104],"scaled":[105],"interconnect":[106],"RC":[107],"parasitics,":[108],"contracts":[110],"layout":[112],"F2F":[115],"footprint.":[117],"addition,":[119],"post-tier-partitioning":[122,156],"optimization":[123,157],"is":[125,140],"shown":[126],"effective":[129],"fixing":[131],"timing":[132],"violations":[133],"caused":[134],"inter-tier":[136],"routing,":[138],"completely":[141],"missing":[142],"S2D.":[144],"Lastly,":[145],"present":[147],"methodology":[149],"recycle":[151],"routing":[153,187],"result":[154],"for":[158],"final":[159],"GDSII":[160],"generation.":[161],"experimental":[163],"results":[164],"show":[165],"at":[167],"iso-performance,":[168],"up":[171],"26.8%":[173],"power":[174],"reduction":[175],"15.6%":[177],"silicon":[178],"area":[179],"savings":[180],"over":[181],"ICs":[184],"without":[185],"resource":[188],"overhead.":[189]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":10},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2018-03-29T00:00:00"}